Achieving higher output current and lower noise is achievable by paralleling two or more LDOs. Implementation must be carefully planned out to optimize performance and minimize output current imbalance.

Because the TPS7A96 output voltage is set by a resistor driven by a current source, the NR/SS resistor and capacitor must be adjusted as per the following:

where:

• n is the number of LDOs in parallel
• I_NR/SS is the NR/SS current as provided in the data sheet Electrical Characteristics table
• C_NR/SS_single is the NR/SS capacitor for a single LDO

When connecting the input and NR/SS pin together, and with the LDO being a buffer, the current imbalance is only affected by the error offset voltage of the error amplifier. As such, the current imbalance can be expressed as:

where:

• ε_I is the current imbalance
• V_OS is the LDO error offset voltage
• R_BALLAST is the ballast resistor
• ΔR_BALLAST is the deviation of the ballast resistor value from the nominal value

With the typical offset voltage of 200 μV, considering no error from the design of the PCB ballast resistor (ΔR_BALLAST = 0) and a 100-mA maximum current imbalance, the ballast resistor must be 4 m? or greater; see Figure 8-16.

Using the configuration described, the LDO output noise is reduced by:

where:

• n is the numbers of LDOs in parallel
• e_{O_single} is the output noise density from a single LDO
• e_{O_parallel} is the output noise density for the resulting parallel LDO

In Figure 8-16, the noise is reduced by 1 / √2.

Figure 8-16 Paralleling Multiple TPS7A96 Devices