ZHCSO36A april 2023 – july 2023 TPS7A96
PRODUCTION DATA
The TPS7A96 is an ultra-low noise (0.5 μVRMS over 10-Hz to 100-kHz bandwidth), ultra-high PSRR (> 50 dB to 2 MHz), high-accuracy (1%), low-dropout (LDO) linear voltage regulator with an input range of 1.9 V to 5.7 V and an output voltage range from 0 V to VIN – VDO and is fully specified above 0.4 VOUT. This LDO regulator uses innovative circuitry to achieve wide bandwidth and high loop gain, resulting in ultra-high PSRR even when operating under very low operational headroom (VIN – VOUT). At a high level, the device has two main blocks (the current reference and the unity-gain LDO buffer) and a few secondary features (such as the precision enable, current limit, and PG pin).
The current reference is controlled by the NR/SS pin. This pin sets the output voltage with a single resistor, sets the start-up time, and filters the noise generated by the reference and external set resistor.
The unity-gain LDO buffer is controlled by the OUT pin. The ultra-low noise does not increase with output voltage and provides wideband PSRR. As such, the SNS pin is only used for remote sensing of the load.
The EN_UV pin sets the precision enable feature. Select the optimal input voltage at which the LDO starts at. There are two independent UVLO voltages in this device: the internal IN rail UVLO and the EN_UV pin.
The FB_PG pin sets the current limit and power-good (PG) features. A voltage divider on this pin programs both the current limit and the PG trip point.
An ultra-low-noise current reference (150 μA, typical) is used in conjunction with an external resistor (RNR/SS) to set the output voltage. This process allows the output voltage range to be set from 0.4 V to (VIN – VDO). To achieve this ultra-low noise, an external capacitor CNR/SS (typically 4.7 μF) is placed in parallel to the RNR/SS resistor used to set the output voltage. The unity-gain architecture provides ultra-high PSRR over a wide frequency range without compromising load and line transients.
This regulator offers programmable current-limit, thermal protection, is fully specified from –40°C to +125°C above 0.4 VOUT, and is offered in a thermally efficient 10-pin, 3-mm × 3-mm WSON package.