Output voltage margining is a technique that allows a circuit to be evaluated for how well changes are tolerated in the power supply. This test is typically performed by adjusting the supply voltage to a fixed percentage above and below its nominal output voltage.

This section discusses the implementation of a voltage margining application using the TPS7A57. A margining target of ±2.5% is used to demonstrate the chosen implementation.

Figure 8-23 shows a simplified visualization of the TPS7A57 REF pin with a current DAC.

Figure 8-23 Simplified Margining Schematic

Table 8-7 summarizes the design requirements.

In this example, the output voltage is set to a nominal 1.8 V using 36 k? at the REF pin to GND. Equation 12 calculates the R_REF resistor value.

The DAC63204, a 4-channel, 12-bit voltage and current output DAC with I²C, was selected and programmed into the current-output mode with an output range set to ±25 μA. In conjunction with the 8-bit current DAC resolution, this output range allows a minimum step size (or LSB) of approximately 196 nA. Into the 36-kΩ resistor, the LSB translates into a 7-mV voltage resolution or 0.38% of the nominal 1.8-V targeted voltage. To achieve the full ±2.5% swing around the nominal voltage, the DAC63204 must source or sink ±1.25 μA.

The current flowing through R_REF changes to 51.25 μA and 48.75 μA and adjusts the output voltage to 1.845 V and 1.75 V, respectively.

Figure 8-24 and Figure 8-25 show the current margining results.

Figure 8-24 Margining Up

Figure 8-25 Margining Down

When implementing voltage margining with this LDO, a time constant is associated with its response. This RC time constant is a result of the parallel combination of R_REF and C_NR/SS, see Figure 8-23. This RC effect is illustrated in Figure 8-24 and Figure 8-25.

Equation 13 calculates the time constant for this implementation:

where:

• R_REF is 36 k?
• C_NR/SS is 4.7 μF
• τ = 169 ms