ZHCSEF7G December 2014 – February 2019 TPS659037
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SYNC CLOCK SPECIFICATION AND DITHER PARAMETERS | ||||||
| ƒ(SYNC) | The allowed range of the external sync clock input | 1.7 | 2.2 | 2.7 | MHz | |
| A(DITHER) | Dither amplitude | 128 | kHz | |||
| M(DITHER) | Dither slope | 1.35 | kHz/µs | |||
| SYNC DC-DC DIGITAL CLOCK INPUT | ||||||
| VIL | Low-level input on SYNCDCDC pin | –0.3 | 0 | 0.3 × VVRTC | V | |
| VIH | High-level input on SYNCDCDC pin | 0.7 × VVRTC | VVRTC | 5.25 | V | |
| Duty cycle of SYNCDCDC input signal | 20% | 80% | ||||
| Hysteresis of input buffer | 0.1 × VVRTC | V | ||||
| SYNC CLOCK AND FREQUENCY FALLBACK | ||||||
| ƒ(FALLBACK) | Fall-back frequency | 1.98 | 2.2 | 2.42 | MHz | |
| ƒ(SAT_LO) | The low saturation frequency output of the PLL | 1.65 | MHz | |||
| ƒ(SAT_HI) | The high saturation frequency output of the PLL | 2.8 | MHz | |||
| ƒ(SETTLE) | Time from initial application or removal of sync clock until PLL output has settled to 1% of its final value | 100 | µs | |||
| ƒ(ERROR) | The steady-state percent difference between fSYNC and the switching frequency | –1% | 1% | |||
| td | Time delay between corresponding staggered phases | 15 | 30 | 45 | ns | |