ZHCSPA4 march 2023 TPS548C26
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY | ||||||
| PVIN operating input range | 4 | 16 | V | |||
| AVIN operating input range | 4 | 16 | V | |||
| IQ(AVIN) | AVIN quiescent current | Non-switching, PVIN = 12 V, AVIN = 12 V, VEN = 2 V, VFB = VREF + 50 mV, no bias on VCC and VDRV pin | 5 | 6.3 | 7.5 | mA |
| ISD(PVIN) | PVIN shutdown supply current | PVIN = 12 V, AVIN = 12 V, VEN = 0 V, no bias on VCC and VDRV pin | 20 | μA | ||
| IVCC | VCC and VDRV external bias current | External 5 V bias on VCC and VDRV pin, regular switching. TJ = 25°C, PVIN = 12 V, IOUT = 35 A, VEN = 2 V, fSW = 0.6 MHz | 32.7 | mA | ||
| IVCC | VCC and VDRV external bias current | External 5 V bias on VCC and VDRV pin, regular switching. TJ = 25°C, PVIN = 12 V, IOUT = 35 A, VEN = 2 V, fSW = 0.8 MHz | 39.7 | mA | ||
| IVCC | VCC and VDRV external bias current | External 5 V bias on VCC and VDRV pin, regular switching. TJ = 25°C, PVIN = 12 V, IOUT = 35 A, VEN = 2 V, fSW = 1.0 MHz | 48.7 | mA | ||
| IVCC | VCC and VDRV external bias current | External 5 V bias on VCC and VDRV pin, regular switching. TJ = 25°C, PVIN = 12 V, IOUT = 35 A, VEN = 2 V, fSW = 1.2 MHz | 57.3 | mA | ||
| ISD(VCC_VDRV) | VCC + VDRV shutdown supply current | External 5 V bias on VCC and VDRV pin, PVIN = 12 V, VEN = 0 V | 5 | 6.3 | 7.5 | mA |
| UVLO | ||||||
| PVINOV | PVIN overvoltage rising threshold | PVIN rising | 18.0 | 18.6 | 19.2 | V |
| PVINOV | PVIN overvoltage falling threshold | PVIN falling. PVIN_OVF status bit, once it is set, cannot be cleared unless PVIN falls below the PVIN overvoltage falling threshold |
12.9 | 13.4 | 13.9 | V |
| PVINUVLO(R) | PVIN UVLO rising threshold | PVIN rising, external 5 V bias on VCC and VDRV pin | 2.35 | 2.55 | 2.75 | V |
| PVINUVLO(F) | PVIN UVLO falling threshold | PVIN falling, external 5 V bias on VCC and VDRV pin | 2.10 | 2.30 | 2.50 | V |
| PVINUVLO(H) | PVIN UVLO hysteresis | 0.25 | V | |||
| ENABLE | ||||||
| VEN(R) | EN voltage rising threshold | EN rising, enable switching | 1.14 | 1.19 | 1.24 | V |
| VEN(F) | EN voltage falling threshold | EN falling, disable switching | 0.94 | 0.98 | 1.02 | V |
| VEN(H) | EN voltage hysteresis | 0.21 | V | |||
| tEN(DIG) | EN Deglitch Time | 0.2 | μs | |||
| EN internal pulldown resistor | VEN = 2 V, EN pin to AGND | 110 | 125 | 140 | k? | |
| INTERNAL VCC LDO | ||||||
| VCC LDO output voltage | AVIN = 4 V, IVCC(load) = 5 mA | 3.925 | 3.97 | 4.0 | V | |
| VCC LDO output voltage | AVIN = 5 V to 16 V, IVCC(load) = 5 mA | 4.28 | 4.44 | 4.55 | V | |
| VCC LDO dropout voltage | AVIN – VVCC, AVIN = 4 V, IVCC(load) = 50 mA | 160.8 | 280 | mV | ||
| VCC_OK rising threshold | TJ = –40°C to 85°C. VCC rising, enabling initial power-on including re-loading default values from NVM | 3.0 | 3.15 | 3.3 | V | |
| VCC_OK falling threshold | TJ = –40°C to 85°C. VCC falling, disabling controller circuit including the memory and the digital engine | 2.95 | 3.10 | 3.25 | V | |
| VCC LDO short-circuit current limit | 150 | mA | ||||
| REFERENCE VOLTAGE | ||||||
| VFB | FB voltage | TJ = 0°C to 85°C | 792 | 800 | 804 | mV |
| VFB | FB voltage | TJ = –40°C to 125°C | 788 | 800 | 808 | mV |
| IFB(LKG) | FB input leakage current | VFB = 800 mV | 10 | nA | ||
| SWITCHING FREQUENCY | ||||||
| fSW(FCCM) | Switching frequency, FCCM operation | TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, RMODE = 0 Ω | 540 | 600 | 660 | kHz |
| fSW(FCCM) | Switching frequency, FCCM operation | TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, RMODE = 1.5 kΩ | 720 | 800 | 880 | kHz |
| fSW(FCCM) | Switching frequency, FCCM operation | TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, RMODE = 14 kΩ | 900 | 1000 | 1100 | kHz |
| fSW(FCCM) | Switching frequency, FCCM operation | TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, RMODE = 16.2 kΩ | 1080 | 1200 | 1320 | kHz |
| fSW(FCCM) | Switching frequency, FCCM operation | TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, RMODE = float | 720 | 800 | 880 | kHz |
| STARTUP AND SHUTDOWN | ||||||
| tON(DLY) | Power on sequence delay | VVCC = 4.5 V | 0.5 | 0.55 | ms | |
| tON(Rise) | Soft-start time | VVCC = 4.5 V, RSS = AGND | 1.0 | 1.1 | ms | |
| tON(Rise) | Soft-start time | VVCC = 4.5 V, RSS = 5.76 k? | 2.0 | 2.2 | ms | |
| tON(Rise) | Soft-start time | VVCC = 4.5 V, RSS = 14 k? | 4.0 | 4.4 | ms | |
| tON(Rise) | Soft-start time | VVCC = 4.5 V, RSS = 28.7 k? | 8.0 | 8.8 | ms | |
| tON(Rise) | Soft-start time | VVCC = 4.5 V, RSS = open | 4.0 | 4.4 | ms | |
| POWER STAGE | ||||||
| RDSON(HS) | High-side MOSFET on-resistance | TJ = 25°C, PVIN = 12 V, VBOOT-SW = 4.5 V | 4 | mΩ | ||
| RDSON(HS) | High-side MOSFET on-resistance | TJ = 25°C, PVIN = 12 V, VBOOT-SW = 5.0 V | 3.91 | mΩ | ||
| RDSON(LS) | Low-side MOSFET on-resistance | TJ = 25°C, PVIN = 12 V, VVDRV = 4.5 V | 1 | mΩ | ||
| RDSON(LS) | Low-side MOSFET on-resistance | TJ = 25°C, PVIN = 12 V, VVDRV = 5 V | 0.98 | mΩ | ||
| tON(min) | Minimum ON pulse width | VVCC = 4.5 V | 60 | ns | ||
| tOFF(min) | Minimum OFF pulse width | VVCC = 4.5 V, IOUT = 1.5 A, VVOSNS = VOUT_Setting – 20 mV, SW falling edge to rising edge | 210 | 250 | ns | |
| BOOT CIRCUIT | ||||||
| IBOOT(LKG) | BOOT leakage current | VEN = 2 V, VBOOT-SW = 5 V | 150 | μA | ||
| VBOOT-SW(UV_F) | BOOT-SW UVLO falling threshold | 2.60 | 2.76 | V | ||
| OVERCURRENT LIMIT | ||||||
| ILS(OCL) | Low-side valley overcurrent limit (TPS548C26) | Valley current limit on LS FET, RILIM = 7.5 k? | 10.2 | 12 | 13.8 | A |
| ILS(OCL) | Low-side valley overcurrent limit (TPS548C26) | Valley current limit on LS FET, RILIM = 12.1 k? | 17.1 | 19 | 20.9 | A |
| ILS(OCL) | Low-side valley overcurrent limit (TPS548C26) | Valley current limit on LS FET, RILIM = 16.2 k? | 23.4 | 26 | 28.6 | A |
| ILS(OCL) | Low-side valley overcurrent limit (TPS548C26) | Valley current limit on LS FET, RILIM = 21.5 k? | 29.7 | 33 | 36.3 | A |
| ILS(OCL) | Low-side valley overcurrent limit (TPS548C26) | Valley current limit on LS FET, RILIM = 24.9 k? | 35.1 | 39 | 42.9 | A |
| ILS(NOC) | Low-side negative overcurrent limit | Sinking current limit on LS FET | –18 | –16 | –14 | A |
| IZC | Zero-cross detection current threshold | ZC comparator threshold, enter DCM. PVIN = 12 V, VVCC = 4.5 V | 1200 | mA | ||
| Response delay before entering Hiccup | 16 | 20 | μs | |||
| Hiccup sleep time before a restart | 49 | 56 | 59 | ms | ||
| OUTPUT OVP AND UVP | ||||||
| VOVF | VOUT Overvoltage-protection (OVP) threshold | (VFB – VGOSNS) and rising | 113.8% | 118.8% | 122.5% | |
| OVF response delay | From OVF detection to the start of the NOC operation | 100 | ns | |||
| VUVF | VOUT Undervoltage-protection (UVP) threshold | (VFB – VGOSNS) and falling | 70% | 75% | 80% | |
| UVF response delay | From UVF detection to tri-state of the power FETs | 16 | 20 | μs | ||
| POWER GOOD | ||||||
| VOL(PG) | PG pin output low-level voltage | IPG = 10 mA, PVIN = 12 V, VVCC = 4.5 V | 300 | mV | ||
| ILKG(PG) | PG pin Leakage current when open drain output is high | Rpullup = 10 k?, VPG = 5 V | 5 | μA | ||
| Minimum VCC for valid PG pin output | PVIN = 0 V, VEN = 0 V, Rpullup = 10 k?, VPG ≤ 0.3 V | 1.2 | V | |||
| OUTPUT DISCHARGE | ||||||
| Output discharge on VOSNS pin | PVIN = 12 V, VVCC = 4.5 V, VVOSNS = 0.5 V, EN=0V | 455 | ? | |||
| THERMAL SHUTDOWN | ||||||
| TJ(SD) | Thermal shutdown (Analog OTP) threshold (1) | Junction temperature rising | 153 | 166 | °C | |
| TJ(HYS) | Thermal shutdown (Analog OTP) hysteresis (1) | 30 | °C | |||