ZHCSPA4 march 2023 TPS548C26
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Internal VCC LDO and Using an External Bias on VCC and VDRV Pin
- 7.3.2 Input Undervoltage Lockout (UVLO)
- 7.3.3 Set the Output Voltage
- 7.3.4 Differential Remote Sense and Feedback Divider
- 7.3.5 Start-up and Shutdown
- 7.3.6 Loop Compensation
- 7.3.7 Set Switching Frequency and Operation Mode
- 7.3.8 Switching Node (SW)
- 7.3.9 Overcurrent Limit and Low-side Current Sense
- 7.3.10 Negative Overcurrent Limit
- 7.3.11 Zero-Crossing Detection
- 7.3.12 Input Overvoltage Protection
- 7.3.13 Output Undervoltage and Overvoltage Protection
- 7.3.14 Overtemperature Protection
- 7.3.15 Power Good
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.4.4 Powering the Device From a Split-rail Configuration
When an external bias that is at a different level from the main VIN bus, is applied to the VDRV pin, the device can be configured to split rail by using both the main VIN bus and the VDRV bias. Connecting a valid bias rail to the VDRV pin overrides the internal VCC LDO, saving power loss on that linear regulator. This configuration helps improve overall system-level efficiency but requires a valid VCC bias. A 5.0-V rail is the common choice for the VDRV bias. With a stable VDRV bias, the VIN input range under this configuration can be as low as 2.7 V and up to 16 V.
The noise of the external bias affects the internal analog circuitry. To ensure a proper operation, a clean, low-noise external bias, and a local decoupling capacitor from the VDRV pin to PGND pin are required. Figure 7-2 shows an example for this split rail configuration.
The VDRV external bias current during nominal operation varies with the bias voltage level and the switching frequency. For example, by setting the device to skip mode, the VDRV pin draws less and less current from the external bias when the switching frequency decreases under light load condition. The typical VDRV external bias current under FCCM operation is listed in the Electrical Characteristics table to help the user prepare the capacity of the external bias.
Under split rail configuration, PVIN, VDRV bias, and EN are the signals to enable the part. For the start-up sequence, it is recommended that the external bias is applied on the VDRV pin earlier than PVIN rail. A practical start-up sequence example is the external 5-V bias is applied first, then the 12-V bus is applied on PVIN, and then EN signal goes high.
Figure 7-2 Split Rail Configuration with
External VCC Bias