5 Pin Configuration and Functions

Figure 5-1 RXX 37-pin WQFN-FCRLF Package (Top View)

Figure 5-2 RXX 37-pin WQFN-FCRLF Package (Bottom View)

Table 5-1 Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
AGND	32	G	Ground pin, reference point for internal control circuitry.
AVIN	3	P	Supply rail for the internal VCC LDO. Connect a 1 μF, 25V ceramic capacitor to AGND to bypass this pin.
BOOT	26	P	Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to PHASE pin. A high temperature (X7R) 0.1 μF or greater value ceramic capacitor is recommended.
DNC	6	—	Do Not Connect (DNC) pin. This pin is the output of internal circuitry and must be floating. Pin 6 and pin 37 can be shorted together but NO any other PCB connection is allowed on pin 6.
EN	27	I	Enable pin, an active-high input pin that, when asserted high, causes the converter to begin the soft-start sequence for the output voltage rail. When de-asserted low, the converter de-asserts PG pin and begins the shutdown sequence of the output voltage rail and continue to completion.
FB	30	I	Positive input of the differential remote sense amplifier, connect to the center point of an external voltage divider. The voltage divider must be connected to output remote sense point.
GOSNS	31	I	Negative input of the differential remote sense circuit, connect to the ground sense point on the load side.
ILIM	1	I	Overcurrent limit selection pin. Connect a resistor to AGND to select the overcurrent limit threshold.
MODE	36	I	The MODE pin selects the switching frequency and sets the operation mode to FCCM or DCM, by connecting a resistor to AGND.
SS	29	I	The SS pin selects the soft-start time, internal compensation and the fault response, by connecting a resistor to AGND.
NC	33, 34, 35	—	No connection (NC) pin. There is no active circuit connected inside the IC. These pins can be connected to ground plane or left open.
NC	37	—	No connection (NC) pin. This pin is floating internally. Pin 37 and pin 6 can be shorted together.
PG	2	O	Power-good output signal. The PG indicator is asserted when the output voltage reaches the regulation. The PG indicator de-asserts low when the EN pin is pulled low or a shutdown fault occurs. This open-drain output requires an external pullup resistor.
PGND	7–10, 19	G	Power ground for the internal power stage.
PHASE	25	—	Return for high-side MOSFET driver. Shorted to SW internally. Connect the bootstrap capacitor from BOOT pin to this pin.
PVIN	20–24	P	Power input for both the power stage. PVIN is the input of the internal VCC LDO as well.
SW	11–18	O	Output switching terminal of the power converter. Connect these pins to the output inductor.
VCC	4	P	Internal VCC LDO output and also the input for the internal control circuitry. A 2.2 μF (or 1 μF), at least 6.3 V rating ceramic capacitor is required to be placed from VCC pin to AGND for decoupling.
VDRV	5	P	Power supply input for gate driver circuit. A 2.2 μF (or 4.7 μF), at least 6.3 V rating ceramic capacitor is required to be placed from VDRV pin to PGND pins to decouple the noise generated by driver circuitry. An external 5 V bias can be connected to this pin to save the power losses on the internal LDO.
VOSNS	28	I	Output voltage sense point for internal on-time generation circuitry. Shorting this pin directly to VOUT sense point is recommended. Adding any resistance higher than 51 Ω between VOUT sense point and the VOSNS pin shifts switching frequency higher than the desired setting. Contact Texas Instruments if a resistor has to be placed between VOUT sense point and the VOSNS pin.

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5 Pin Configuration and Functions