ZHCSPA4 march 2023 TPS548C26
PRODUCTION DATA
A PVIN UVLO circuit monitors the PVIN level and turns of switching when PVIN level is insufficient. When the PVIN pin voltage is lower than the PVINUVLO falling threshold voltage (typically 2.30 V), the device stops switching and discharges the internal DAC reference. After the PVIN voltage increases beyond the PVINUVLO rising threshold voltage (typically 2.55 V), the device re-initiates the soft-start and switches again. This PVIN UVLO is a non-latch protection.
When the internal VCC LDO is used to power the VCC and VDRV pins, the device switching is not gated by this PVIN UVLO. When the PVIN drops below the level of VDRV UVLO falling threshold plus the LDO dropout voltage, the VDRV UVLO is triggered and the switching stops. When PVIN rises, the PVIN level has to rise above the VDRV UVLO rising threshold to enable the switching. This means using the internal VCC LDO does not allow power conversion under ultra-low PVIN condition.
While, power conversion under ultra-low PVIN condition can be enabled with an external 5-V bias on VCC and VDRV pins. This configuration allows power conversion under ultra-low PVIN condition down to 2.7 V, as long as the external bias maintains at a 5-V level to satisfy both the VCC_OK UVLO and the VDRV UVLO.