Startup

The startup sequence includes three sequential periods. During the first period, the device does initialization which includes building up internal LDOs and references, register value initialization, pin strap detection, enabling digital interface, and so forth. The initialization, which is not gated by EN pin voltage, starts as long as VCC/VDRV pin voltage is above the VCC UVLO rising threshold (3.2-V typical). The length of this period is about 200 μs for TPS544C26 device. The I²C communication including both read and write operations is allowed after finishing the initialization.

Once the EN pin voltage crosses above EN high threshold (typically 1.2 V) the device moves to the second period, power-on delay. The power-on delay is programmable in TPS544C26 through register Section 7.6.20 with minimum 0.5 ms delay and maximum 2 ms delay.

The V_OUT soft-start is the third period. A soft-start ramp, which is an internal signal, starts when the chosen power-on delay finishes. The soft-start time can be selected in register Section 7.6.21 with options of 1 ms, 2 ms, 4 ms, 8 ms, and 16 ms. When starting up without pre-bias on the output, the VOUT ramps up from 0 V to either the selected Vboot value or the programmabled VOUT_CMD value (depending on the VOUT_CTRL setting) to avoid the inrush current by the output capacitor charging, and also minimize VOUT overshoot. The VOUT ramping up slew rate is determined by VOUT step (set by PROTOCOL_ID in register (C2h) PROTOCOL_ID_SVID, Vboot and TON_RISE values, and the actual soft-start time can vary from the selected TON_RISE value. Table 7-7 shows more details.

For the startup with a pre-biased output the device limits current from being discharged from the prebiased output voltage by preventing the low-side FET from forcing the SW node low until after the first PWM pulse turns on the high-side FET. Once the increasing reference voltage exceeds the feedback voltage which is internally divided down from (VOSNS?GOSNS) level, the high-side SW pulses start. This enables a smooth startup with a pre-biased output.

Once VOUT reaches the regulation value and VRRDY delay expires, the converter asserts VRRDY pin and becomes ready for SVID commands. The VRRDY delay can be programmed in (A0h) SYS_CFG_USER1 register and the default value is set to 0 ms to meet SVID communication requirement.

Shutdown

The TPS544C26 device also offers programmable soft-stop feature through I2C register (65h) TOFF_FALL with 0.5 ms, 1 ms, 2 ms, and 4 ms options. The soft-stop feature force a controlled decrease of the output voltage from regulation to 200 mV. Once Vout is discharged to 200 mV level the power stage stops switching and goes to tri-state. There can be negative inductor current forced during the TOFF_FALL time to discharge the output voltage. This feature can be enabled or disabled through I2C. Configuring EN_SOFT_STOP bit in register Section 7.6.36 to value “0” disables the soft-stop feature and automatically sets TOFF_DELAY to 0 ms.

In the case of Soft-stop is enabled, after a stop condition is received and the selected TOFF_DELAY delay expires, the TPS544C26 device enters the soft-stop operation during which the control loop actively controls the discharge slew rate of the output voltage. The power stage continues switching while the internal reference ramps down linearly. The discharge slew rate during this phase is determined by the selected boot up voltage (not the current output voltage) and the selected TOFF_FALL time. Once Vout is discharged to 200 mV level the power stage stops switching and goes to tri-state. The Vout discharge continues but the discharge slew rate is controlled by the load current. With this discharge operation, the TPS544C26 device controls the soft-stop slew rate rather the total soft-stop time, thus the total VOUT discharge time (a.k.a soft-stop time) can vary from the register (65h) TOFF_FALL value. Another word, The TOFF_FALL time is utilized to set the internal reference DAC ramp-down time from the regulation level to 0 mV. For example, under heavy load condition, the total soft-stop time from VOUT regulation level to zero volt is likely shorter than the programmed TOFF_FALL value. Under light load, the total soft-stop time likely becomes longer than the programmed TOFF_FALL value. Table Table 7-8 shows more details.

In the case of soft-stop feature is disabled through the EN_SOFT_STOP bit in (A0h) SYS_CFG_USER1 register, both high-side and low-side FET drivers are turned off immediately at the time when a stop condition is received (as programmed by the (02h) ON_OFF_CONFIG command), and the output voltage discharge slew rate is controlled by the external load.