ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| CMD Address | 61h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Backup: | EEPROM or Pin Detection |
| Updates: | On-the-fly |
The TON_RISE command sets the time, in milliseconds, from when the output starts to rise until the voltage has entered the regulation band, which effectively sets the slew rate of the reference DAC during the soft-start period. Note that the soft-start time is equal to TON_RISE selection only when the output voltage is controlled by SVID bus. The soft-start time varies from the TON_RISE selection when I2C_OFFSET is involved or (A6h) VOUT_CMD is used for boot up. See section Startup and Table 7-7 for more details.
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R | R | R | R/W | R/W | R/W |
| Reserved | TON_RISE | ||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7:3 | Reserved | R | 00000b | Not used and always set to 0. |
| 2:0 | TON_RISE | R/W | NVM | These bits select the
soft-start time options. 000b: TON_RISE time = 1 ms 001b: TON_RISE time = 2 ms 010b: TON_RISE time = 4 ms 011b: TON_RISE time = 8 ms 100b to 111b: TON_RISE time = 16 ms |