Layout is critical for good power-supply design. Layout example shows the recommended PCB-layout configuration. A list of PCB layout considerations using the device is listed as follows:

• Place the power components (including input and output capacitors, the inductor, and the IC) on the top side of the PCB. To shield and isolate the small signal traces from noisy power lines, insert at least one solid ground inner plane.
• PVIN-to-PGND decoupling capacitors are important for FET robustness. Besides the large volume 0603 or 0805 ceramic capacitors, TI highly recommends a 0.1-μF 0402 ceramic capacitor with 25 V / X7R rating on PVIN pin 20 (top layer) to bypass any high frequency current in PVIN to PGND loop. The 25-V rating is recommended but can be lowered to 16-V rating for an application with tightly regulated 12-V input bus.
• When one or more PVIN-to-PGND decoupling capacitors are placed on bottom layer, extra impedance is introduced to bypass IC PVIN node to IC PGND node. Placing at least 3 times PVIN vias on PVIN pad (formed by pin 20 to pin 24) and at least 9 times PGND vias on the thermal pad (underneath of the IC) is important to minimize the extra impedance for the bottom layer bypass capacitors.
• Except the PGND vias underneath the thermal pad, at least 4 PGND vias are required to be placed as close as possible to the PGND pin 7 to pin 10. At least 2 PGND vias are required to be placed as close as possible to the PGND pin 19. Thisaction minimizes PGND bounces and also lowers thermal resistance.
• Place the VCC/VDRV-to-PGND decoupling capacitor as close as possible to the device. TI recommends a2.2-μF/6.3-V/X7R/0603 or 4.7-μF/6.3-V/X6S/0603 ceramic capacitor. The voltage rating of this bypass capacitor must be at least 6.3 V but no more than 10 V to lower ESR and ESL. The recommended capacitor size is 0603 to minimize the capacitance drop due to DC bias effect. Ensure the VCC/VDRV to PGND decoupling loop is the smallest and ensure the routing trace is wide enough to lower impedance.
• For remote sensing, the connections from the VOSNS/GOSNS pins to the remote location must be a pair of PCB traces with at least 12 mil trace width, and must implement Kelvin sensing across a high bypass capacitor of 0.1 μF or higher. The ground connection of the remote sensing signal must be connected to GOSNS pin. The VOUT connection of the remote sensing signal must be connected to the VOSNS pin. To maintain stable output voltage and minimize the ripple, the pair of remote sensing lines must stay away from any noise sources such as inductor and SW nodes, or high frequency clock lines. And TI recommends to shield the pair of remote sensing lines with ground planes above and below.
• For single-end sensing, connect the VOSNS pin to a high-frequency local bypass capacitor of 0.1 μF or higher, and short GOSNS to AGND with shortest trace.
• To minimize the impact from switching noise and achieve high accuracy on the input power monitoring feature, a PGND referenced bypass capacitor is required for each of VINSENP and VINSENM pins, with at least 100-pF volume and at least 25-V rating. These bypass capacitors must be placed close to VINSENP or VINSENM pin accordingly.
• In a case that the input power feature is not used, follow below connection for pin 3 VINSENP and pin 4 VINSENM so that the device can report the input voltage level on PVIN node:
  1. Short pin 3 VINSENP to pin 4 VINSENM,
  2. Place a 0.1 μF ceramic bypass capacitor on pin 4 VINSENM referring to AGND,
  3. Connect pin 4 VINSENM to PVIN node of TPS544C26 device.
• The AGND pin 32 must be connected to a solid PGND plane. TI recommends to place two AGND vias close to pin 32 to route AGND from top layer to bottom layer, and then connect the AGND trace to the PGND vias (underneath IC) through either a net-tie or a 0 ? resistor on the bottom layer.
• Connecting a resistor from pin 29 (I²C_ADDR) to AGND sets I²C address. It is required not to have any capacitor on pin 29. A capacitor on pin 29 likely leads to a wrong detection result for I²C address.
• Pin 6 (DNC) is a Do-Not-Connect pin. Pin 6 can be shorted to pin 37, which is an NC pin (No internal Connection). Do not connect pin 6 to any other net including ground.