ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| CMD Address | 7Bh |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Backup: | No |
| Updates: | On-the-fly |
The STATUS_IOUT command returns one data byte with contents as follows. All supported bits can be cleared either by CLEAR_FAULTS, or individually by writing a "1" to the (7Bh) STATUS_IOUT register in their position. If a fault condition is still present when the corresponding bit is cleared, the fault bit is immediately set again.
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R/W | R | R | R | R | R | R |
| IOUT_OCL | IOUT_OCUV | 0 | 0 | 0 | 0 | 0 | 0 |
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | IOUT_ OCL | R | 0b |
0b: Latched flag indicating low-side valley OC limit has not occurred. 1b: Latched flag indicating low-side valley OC limit has occurred. |
| 6 | IOUT_OCUV | R/W | 0b |
0b: Latched flag indicating both low-side valley OC limit and VOUT Tracking UV fault have not occurred. 1b: Latched flag indicating both low-side valley OC limit and VOUT Tracking UV fault have occurred. |
| 5:0 | Not supported | R | 000000b | Not supported and always set to 0. |