ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| CMD Address | A7h |
| Write Transaction: | N/A |
| Read Transaction: | Read Byte |
| Format: | VID, either 5 mV/LSB or 10 mV/LSB |
| NVM Backup: | No |
| Update Rate: | 190 μs |
| Supported Range: | 8 V – 16 V |
The VID_SETTING command returns the last commanded VOUT level either from I2C or from SVID including Vboot. The reading in this register is “in sync” with the SVID (31h) VID_SETTING register. This register does not include any OFFSET contributions from either SVID or I2C space.
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R | R | R | R | R | R |
| VID_SETTING | |||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7:0 | VID_SETTING | R | Last commanded VOUT | These bits tells the last commanded VOUT (VID format). |