ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| Register Address | A0h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Back-up: | EEPROM |
| Updates: | On-the-fly. Note that many of the fields in this register either require the output to be disabled to take effect or require (15h) STORE_USER_ALL then VCC reset. |
The SYS_CFG_USER1 command contains miscellaneous bits for the device configuration.
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| FCCM | VOUT_CTRL | EN_SOFT_STOP | VRRDY_DELAY | OVRD_SVID_ADDR | OVRD_I2C_ADDR | ||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | FCCM(1) | R/W | NVM |
0b: Discontinuous conduction mode (DCM) operation at light loads. 1b: Forced continuous conduction mode (FCCM) operation at light loads. |
| 6:5 | VOUT_CTRL(1) | R/W | NVM |
00b: Output voltage and offset are programmed through the SVID interface. Writes to I2C register (A6h) VOUT_CMD are always accepted but do not change the output voltage. Writes to (A8h) I2C_OFFST are always NACKed. 01b: Output voltage is programmed through the SVID interface and offset is programmed through the I2C interface (A8h) I2C_OFFST. Writes to SVID (33h) OFFSET register are always accepted but do not change the output voltage. 10b: Output voltage and offset are controlled via I2C register (A6h) VOUT_CMD and (A8h) I2C_OFFST, respectively. Writes to SVID (33h) OFFSET register or SetVID commands are always accepted but do not change the output voltage. 11b: Same as 10b. |
| 4 | EN_SOFT_STOP(1) | R/W | NVM |
0b: The SW switching is turned off immediately (ignores TOFF_FALL (soft-stop) and TOFF_DELAY is automatically set to 0 ms). 1b: The SW switching is turned off after going through TOFF_DELAY and TOFF_FALL (soft-stop). |
| 3:2 | VRRDY_DELAY(1) | R/W | NVM | Program the rising edge delay time from soft start complete to
VRRDY pin going high: 00b: 0 ms 01b: 0.5 ms 10b: 1.0 ms 11b: 2.0 ms |
| 1 | OVRD_SVID_ADDR(2) | R/W | NVM | This bit is reserved for future usage. |
| 0 | OVRD_I2C_ADDR(2) | R/W | NVM |
0b: I2C address is determined by pin-strapping on the I2C_ADDR pin. 1b: I2C address is determined by NVM backup. |