ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| Register Address | A6h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | VID, either 5 mV/LSB or 10 mV/LSB |
| NVM Back-up: | EEPROM |
| Updates: | On-the-fly |
If the VOUT_CTRL bits in (A0h) SYS_CFG_USER1 are set to 10b, VOUT_CMD causes the device to set its output voltage to the commanded value. Output voltage changes due to VOUT_CMD occur at ? of the fast slew rate which is selected in (AFh) DVS_CFG register.
The VOUT step (LSB) is either 5 mV/LSB or 10 mV/LSB which is determined by PROCOTOL_ID bits in (C2h) PROTOCOL_ID_SVID register.
The device will NACK writes to VOUT_CMD during soft-start and soft-stop. The device will ACK writes to VOUT_COMMAND after soft-start has completed. After soft-start has completed, writes to VOUT_CMD are also allowed even if the output voltage is still transitioning to a previously programmed VOUT_CMD. The output voltage will immediately begin transitioning to the newly programmed VOUT_CMD at the ? of the fast slew rate which is selected in (AFh) DVS_CFG register. The device does not wait for the prior transition to completed.
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| VOUT_CMD | |||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7:0 | VOUT_CMD | R/W | NVM | Sets the output voltage target via the I2C interface. See Table 7-6 for the available values. |