ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| Register Address | A8h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | DIRECT |
| NVM Back-up: | EEPROM |
| Updates: | on-the-fly |
The I2C_OFFSET is used to apply a fixed offset voltage to the output voltage command value. Output voltage changes due to I2C_OFFSET occur at ? of the fast slew rate which is selected in (AFh) DVS_CFG register..
The usage of I2C_OFFSET depends on the value of VOUT_CTRL in (A0h) SYS_CFG_USER1 register. See Table 7-4 for more details.
When the PROTOCOL_ID bits in (C2h) PROTOCOL_ID_SVID is 01b or 10b (VOUT step = 5 mV), the I2C_OFFSET adds offset to the output voltage with the 0.5 mV/LSB. With a signed implementation, the offset can be programmed in a range of ?64 mV to +63 mV.
When the PROTOCOL_ID bits in (C2h) PROTOCOL_ID_SVID is 00b or 11b (VOUT step = 10 mV), the I2C_OFFSET adds offset to the output voltage with the 1.0 mV/LSB. With a signed implementation, the offset can be programmed in a range of ?128 mV to +127 mV.
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| I2C_OFFSET | |||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7:0 | I2C_OFFSET | R/W | NVM | Output voltage offset with Direct format. VOUT step = 5 mV configuration: I2C OFFSET is 0.5 mV/LSB, with a range of ?64 mV to +63 mV. VOUT step = 10 mV configuration: I2C OFFSET is 1.0 mV/LSB, with a range of ?128 mV to +127 mV. |