ZHCSLK6B July 2021 – February 2025 TPS1HC100-Q1
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SNS TIMING - CURRENT SENSE | ||||||
| tSNSION1 | Settling time from rising edge of DIA_EN 50% of VDIA_EN to 90% of settled ISNS |
VENx= 5 V, VDIA_EN = 0 V to 5 V RSNS = 1 kΩ, IL = 1A |
30 | μs | ||
| tSNSION1 | Settling time from rising edge of DIA_EN 50% of VDIA_EN to 90% of settled ISNS |
VEN = 5 V, VDIA_EN = 0 V to 5 V RSNS = 1 kΩ, IL = 30 mA |
30 | μs | ||
| tSNSION2 | Settling time from rising edge of EN and DIA_EN 50% of VDIA_EN VEN to 90% of settled ISNS |
VEN = VDIA_EN = 0 V to 5 V VBB = 13.5V RSNS = 1 kΩ, RLOAD = 10? |
150 | μs | ||
| tSNSION3 | Settling time from rising edge of EN with DIA_EN HI; 50% of VDIA_EN VEN to 90% of settled ISNS |
VEN = 0 V to 5 V, VDIA_EN = 5 V VBB = 13.5V RSNS = 1 kΩ, RLOAD = 10? |
150 | μs | ||
| tSNSIOFF | Settling time from falling edge of DIA_EN | VEN = 5 V, VDIA_EN = 5 V to 0 V VBB = 13.5V RSNS = 1 kΩ, RL = 10 Ω |
20 | μs | ||
| tSETTLEH | Settling time from rising edge of load step | VEN = 5 V, VDIA_EN = 5 V RSNS = 1 kΩ, IOUT = 0.5 A to 3 A |
20 | μs | ||
| tSETTLEL | Settling time from falling edge of load step | VEN = 5 V, VDIA_EN = 5 V RSNS = 1 kΩ, IOUT = 3 A to 0.5 A |
20 | μs | ||