x8x8拨牐拨牐x8免费视频8午夜天天摸天天碰天天添中文无码 ,欧美做爰猛烈大尺度电影在线,制服国产欧美亚洲日韩

SNVSBY3A November 2020 – April 2021 TLV840-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

DBV|5
- MPDS018T

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7.5 Electrical Characteristics

At 0.7 V ≤ V_DD ≤ 6 V, CT = MR = Open, RESET pull-up resistor (R_pull-up) = 100 kΩ to VDD, output reset load (C_LOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 100 mV/μs. Typical values are at T_A = 25℃

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
COMMON PARAMETERS
V_DD	Input supply voltage	TLV840MAxL	0.7		6	V
V_IT–	Negative-going input threshold accuracy ⁽¹⁾	V_IT- = 0.8 V to 1.7 V	–2.5	±0.5	2.5	%
V_IT–	Negative-going input threshold accuracy ⁽¹⁾	V_IT- = 1.8 V to 5.4 V	–2	±0.5	2	%
V_HYS	Hysteresis on V_IT– pin		2.5	5	7	%
I_DD	Supply current into VDD pin ⁽²⁾	V_DD = 2 V; V_IT– = 0.8 V to 1.8 V		0.12	1.0	μA
I_DD	Supply current into VDD pin ⁽²⁾	V_DD = 6 V; V_IT– = 0.8 V to 5.4 V		0.15	1.2	μA
V_{MR_L}	Manual reset logic low input ⁽²⁾				0.3V_DD	V
V_{MR_H}	Manual reset logic high input ⁽²⁾		0.7V_DD			V
R_MR	Manual reset internal pull-up resistance			100		kΩ
R_CT	CT pin internal resistance			500		kΩ
TLV840MADL (Open-drain active-low)
V_POR	Power on Reset Voltage ⁽³⁾	V_OL(max) = 300 mV I_OUT(Sink) = 15 μA			700	mV
V_OL	Low level output voltage	V_DD = 0.7 V, 0.8 V ≤ V_IT– ≤ 1.5 V I_OUT(Sink) = 15 μA			300	mV
		V_DD =1.5 V, 1.6 V ≤ V_IT– ≤ 3.3 V I_OUT(Sink) = 500 μA			300
		V_DD = 3.3 V, 3.4 V ≤ V_IT– ≤ 5.5 V I_OUT(Sink) = 2 mA			300
I_lkg(OD)	Open-Drain output leakage current	V_DD = V_PULLUP = 6V T_A = –40℃ to 85℃		10	100	nA
I_lkg(OD)	Open-Drain output leakage current	V_DD = V_PULLUP = 6V		10	350	nA
TLV840MAPL (Push-pull active-low)
V_POR	Power on Reset Voltage ⁽³⁾	V_OL(max) = 300 mV I_OUT(Sink) = 15 μA			700	mV
V_OL	Low level output voltage	V_DD = 0.7 V, 0.8 V ≤ V_IT– ≤ 1.5 V I_OUT(Sink) = 15 μA			300	mV
		V_DD = 1.5 V, 1.6 V ≤ V_IT– ≤ 3.3 V I_OUT(Sink) = 500 μA			300
		V_DD = 3.3 V, 3.4 V ≤ V_IT– ≤ 5.5 V I_OUT(Sink) = 2 mA			300
V_OH	High level output voltage	V_DD= 1.8 V, 0.8 V ≤ V_IT– ≤ 1.4 V I_OUT(Source) = 500 μA	0.8V_DD			V
		V_DD= 3.3 V, 1.5 V ≤ V_IT– ≤ 3.0 V I_OUT(Source) = 500 μA	0.8V_DD
		V_DD= 6 V, 3.1 V ≤ V_IT– ≤ 5.5 V I_OUT(Source) = 2 mA	0.8V_DD
TLV840MAPH (Push-pull active-high)
V_POR	Power on Reset Voltage ⁽³⁾	V_OH(min) = 0.8V_DD V I_{OUT (Source)} = 15 uA			900	mV
V_OL	Low level output voltage	VDD=3.3 V 0.8 V ≤ V_IT- ≤ 3.0 V I_OUT(Sink) = 500 μA			300	mV
V_OL	Low level output voltage	VDD=6 V 3.1 V ≤ V_IT- ≤ 5.5 V I_OUT(Sink) = 2 mA			300	mV
V_OH	High level output voltage	VDD = 0.9 V 1 V ≤ V_IT- ≤ 1.5 V I_OUT(Sink) = 15 μA	0.8V_DD			V
		VDD=1.5 V 1.6 V ≤ V_IT- ≤ 3.3 V I_OUT(Sink) = 500 μA	0.8V_DD			V
		VDD=3.3 V 3.4 V ≤ V_IT- ≤ 5.5 V I_OUT(Sink) = 2 mA	0.8V_DD			V

(1) V_IT– threshold voltage range from 0.8 V to 5.4 V (for DL, PL versions) in 100 mV steps

(2) If the logic signal driving MR is less than VDD, then I_DDcurrent increases based on voltage differential

(3) V_POR is the minimum V_DD voltage level for a controlled output state