_{(1) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then tD programmed time will be
added to the startup time, VDD slew rate = 100 mV / μs.}

_{(2) Open-Drain timing diagram where RESET is pulled up to VDD via an external pull-up resistor}

_{(3) RESET output is undefined when VDD is < VPOR}

_{(4) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then tD programmed time will be
added to the startup time, VDD slew rate = 100 mV / μs.}

_{(5) RESET output is undefined when VDD is < VPOR and limited to VOL for VDD slew rate = 100 mV / μS}

_{(6) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then tD programmed time will be
added to the startup time, VDD slew rate = 100 mV / μs.}