RESET (Active-Low) applies to TLV840DL-Q1 (Open-Drain) and TLV840PL-Q1 (Push-Pull) hence the "L" in the device name. RESET remains high (deasserted) as long as VDD is above the negative threshold (V_IT-) and the MR pin is floating or above V_{MR_H}. If VDD falls below the negative threshold (V_IT-) or if MR is driven low, then RESET is asserted.

When MR is again logic high or floating and VDD rise above V_IT+, the delay circuit will hold RESET low for the specified reset time delay (t_D). When the reset time delay has elapsed, the RESET pin goes back to logic high voltage (V_OH).

The TLV840DL-Q1 (Open-Drain) version, denoted with "D" in the device name, requires an external pull-up resistor to hold RESET pin high. Connect the external pull-up resistor to the desired pull-up voltage source and RESET can be pulled up to any voltage up to 6.5 V independent of the VDD voltage. To ensure proper voltage levels, give some consideration when choosing the pull-up resistor values. The external pull-up resistor value determines the actual V_OL, the output capacitive loading, and the output leakage current (I_lkg(OD)).

The Push-Pull variants (TLV840PL-Q1 and TLV840PH-Q1), denoted with "P" in the device name, does not require an external pull-up resistor.