SNVSBY3A November 2020 – April 2021 TLV840-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| tP_HL | Propagation detect delay for VDD falling below VIT– | VDD : (VIT+ + 10%) to (VIT– – 10%)(1) | 30 | 50 | μs | ||
| tD | Reset time delay | CT pin = Open or NC (VIT- - 10%) to (VIT+ + 10%) |
40 | 80 | μs | ||
| CT pin = 10 nF | 6.2 | ms | |||||
| CT pin = 1 μF | 619 | ms | |||||
| tGI_VIT– | Glitch immunity VIT– | 5% VIT– overdrive(2) | 10 | μs | |||
| tSTRT | Startup Delay (3) | CT pin = Open or NC |
300 | μs | |||
| t MR_PW | MR pin pulse duration to assert reset (4) | 500 | ns | ||||
| t MR_RES | Propagation delay from MR low to reset assertion | VDD = 3.3 V, MR = V MR_H to V MR_L |
1 | μs | |||
| t MR_tD | Delay from MR release to reset deassert | VDD = 3.3 V, MR = V MR_L to V MR_H |
tD | ms | |||