ZHCSRJ6D June 2010 – October 2024 TLV320AIC3104-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Switching Characteristics I2S/LJF/RJF Timing in Master Mode
- 6.7 Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
- 6.8 Switching Characteristics DSP Timing in Master Mode
- 6.9 Switching Characteristics DSP Timing in Slave Mode
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Audio Data Converters
- 7.3.2 Stereo Audio ADC
- 7.3.3 Automatic Gain Control (AGC)
- 7.3.4 Stereo Audio DAC
- 7.3.5 Digital Audio Processing for Playback
- 7.3.6 Digital Interpolation Filter
- 7.3.7 Delta-Sigma Audio DAC
- 7.3.8 Audio DAC Digital Volume Control
- 7.3.9 Analog Output Common-mode Adjustment
- 7.3.10 Audio DAC Power Control
- 7.3.11 Audio Analog Inputs
- 7.3.12 Analog Input Bypass Path Functionality
- 7.3.13 ADC PGA Signal Bypass Path Functionality
- 7.3.14 Input Impedance and VCM Control
- 7.3.15 MICBIAS Generation
- 7.3.16 Analog Fully Differential Line Output Drivers
- 7.3.17 Analog High-Power Output Drivers
- 7.3.18 Short-Circuit Output Protection
- 7.3.19 Jack and Headset Detection
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Register Maps
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
訂購信息
5 Pin Configuration and Functions
NOTE: Connect
the device thermal pad to DRVSS.
Table 5-1 Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AVDD | 25 | — | Analog DAC voltage supply, 2.7 V to 3.6 V |
| AVSS1 | 17 | — | Analog ADC ground supply, 0 V |
|
AVSS2 |
26 |
— | Analog DAC ground supply, 0 V |
| BCLK | 2 | I/O | Audio serial data bus bit clock input/output |
| DIN | 4 | I | Audio serial data bus data input |
| DOUT | 5 | O | Audio serial data bus data output |
| DRVDD | 18 | — | Analog ADC and output driver voltage supply, 2.7 V to 3.6 V |
|
DRVDD |
24 |
— | Analog output driver voltage supply, 2.7 V to 3.6 V |
| DRVSS | 21 | — | Analog output driver ground supply, 0 V |
| DVDD | 32 | — | Digital core voltage supply, 1.525 V to 1.95 V |
| DVSS | 6 | — | Digital core / I/O ground supply, 0 V |
| HPLCOM | 20 | O | High-power output driver (left –, or multifunctional) |
| HPLOUT |
19 |
O | High-power output driver (left +) |
|
HPRCOM |
22 |
O |
High-power output driver (right –, or multifunctional) |
|
HPROUT |
23 |
O |
High-power output driver (right +) |
| IOVDD | 7 | — | Digital I/O voltage supply, 1.1 V to 3.6 V |
| LEFT_LOM | 28 | O | Left line output (–) |
| LEFT_LOP | 27 | O | Left line output (+) |
| MCLK | 1 | I | Master clock input |
| MIC1LM/LINE1LM | 11 | I | Left input – (diff only) |
| MIC1LP/LINE1LP | 10 | I | Left input 1 (SE) or left input + (diff) |
| MIC1RM/LINE1RM | 13 | I | Right input – (diff only) |
| MIC1RP/LINE1RP | 12 | I | Right input 1 (SE) or right input + (diff) |
| MIC2L/LINE2L/MICDET | 14 | I | Left input 2 (SE); can support microphone detection |
| MIC2R/LINE2R | 16 | I | Right input 2 (SE) |
| MICBIAS | 15 | O | Microphone bias voltage output |
| RESET | 31 | I | Reset |
| RIGHT_LOM | 30 | O | Right line output (–) |
| RIGHT_LOP | 29 | O | Right line output (+) |
| SCL | 8 | I/O | I2C serial clock input |
| SDA | 9 | I/O | I2C serial data input/output |
| WCLK | 3 | I/O | Audio serial data bus word clock input/output |