ZHCSRJ6D June 2010 – October 2024 TLV320AIC3104-Q1
PRODUCTION DATA
All specifications at 25°C, DVDD = 1.8 V. See Figure 6-4
| PARAMETR | IOVDD = 1.1 V | IOVDD = 3.3 V | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| tH(BCLK) | BCLK high period | 70 | 35 | ns | ||
| tL(BCLK) | BCLK low period | 70 | 35 | ns | ||
| ts(WS) | ADWS, WCLK setup time | 10 | 8 | ns | ||
| th(WS) | ADWS/WCLK hold time | 10 | 8 | ns | ||
| td(DO-BCLK) | BCLK to DOUT delay time | 50 | 20 | ns | ||
| ts(DI) | DIN setup time | 10 | 6 | ns | ||
| th(DI) | DIN hold time | 10 | 6 | ns | ||
| tr | Rise time | 8 | 4 | ns | ||
| tf | Fall time | 8 | 4 | ns | ||
Figure 6-1 I2S/LJF/RJF Timing in Master Mode
Figure 6-2 I2S/LJF/RJF Timing in Slave Mode
Figure 6-3 DSP
Timing in Master Mode
Figure 6-4 DSP
Timing in Slave Mode