ZHCSMM9A December 2020 – June 2021 TLV320ADC6120
PRODUCTION DATA
If the host device exits sleep mode by setting the SLEEP_ENZ bit to 1'b1, the device enters active mode. In active mode, I2C transactions can be done to configure and power-up the device for active operation. After entering active mode, wait at least 1 ms before starting any I2C transactions in order to allow the device to complete the internal wake-up sequence.
Read and write operations to the programmable coefficient registers in page 2, page 3, and page 4, and to the channel configuration registers (CHx_CFG[1:4]), DRE_CFG0, and AGC_CFG0 in page 0 must be done 10 ms after exiting sleep mode.
After configuring all other registers for the target application and system settings, configure the input and output channel enable registers, IN_CH_EN (P0_R115) and ASI_OUT_CH_EN (P0_R116), respectively. Lastly, configure the device power-up register, PWR_CFG (P0_R117). All programmable coefficient values must be written before powering up the respective channel.
In active mode, the power-up and power-down status of various blocks is monitored by reading the read-only device status bits located in the DEV_STS0 (P0_R117) and DEV_STS1 (P0_R118) registers.