ZHCSPI8D November 2021 – July 2022 TLC6984
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Independent and Stackable Mode
- 8.3.2 Current Setting
- 8.3.3 Frequency Multiplier
- 8.3.4 Line Transitioning Sequence
- 8.3.5 Protections and Diagnostics
- 8.4 Device Functional Modes
- 8.5 Continuous Clock Series Interface
- 8.6 PWM Grayscale Control
- 8.7 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- RRF|76
訂購信息
8.5.2 CCSI Frame Format
Figure 8-17 defines the format of the command and data transimission. There are four states in one frame.
- IDLE: SCLK is always existent and continuous, and DIN is always HIGH.
- START: DIN changes from HIGH to LOW after the IDLE states.
- DATA:
- Head_bytes: command identifier that contains one 16-bit data and one check bit. It can be WRITE COMMAND ID or READ COMMAND ID (see Register Maps for more details).
- Data_bytes_N: The Nth data-bytes, contains 3 × 17-bit data, each 17-bit data contains one 16-bit data and one check bit. N is the number of devices cascaded in a data chain.
- END: the device recognizes continuous 18-bit HIGH on DIN, then returns to IDLE state.
- CHECK BIT: the check bit (17th bit) value is the NOT of 16th bit value, to avoid continuous 18-bit HIGH (to distinguish with END).
Figure 8-17 CCSI FrameThe IDLE state is not the necessary, that means the START state of next frame can connect to the END state of current frame.