ZHCSPI8D November 2021 – July 2022 TLC6984
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Independent and Stackable Mode
- 8.3.2 Current Setting
- 8.3.3 Frequency Multiplier
- 8.3.4 Line Transitioning Sequence
- 8.3.5 Protections and Diagnostics
- 8.4 Device Functional Modes
- 8.5 Continuous Clock Series Interface
- 8.6 PWM Grayscale Control
- 8.7 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RRF|76
訂購信息
9.2.2 Detailed Design Procedure
Figure 9-3 gives a detail design procedure for LED display. After power on and digital signals are ready, the first step for the controller is to send the chip index command to let the devices know their identifications. Then, the controller sends the configuration data to the FC registers. After this, it sends the VSYNC at the beginning of each frame and also sends the data to each device. The devices display the data of last frame when the VSYNC comes and meanwhile receive the data of current frame transmitted from controller. The registers can be read at anytime of the frame.
Figure 9-3 Design Procedure for LED Display