ZHCSGQ0A September 2017 – February 2022 TIC10024-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VS Pin
- 8.3.2 VDD Pin
- 8.3.3 Device Initialization
- 8.3.4 Device Trigger
- 8.3.5 Device Reset
- 8.3.6 VS Under-Voltage (UV) Condition
- 8.3.7 VS Over-Voltage (OV) Condition
- 8.3.8 Switch Inputs Settings
- 8.3.9 Interrupt Generation and INT Assertion
- 8.3.10 Temperature Monitor
- 8.3.11 Parity Check And Parity Generation
- 8.3.12 Cyclic Redundancy Check (CRC)
- 8.4 Device Functional Modes
- 9 Programming
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
10.2.3 Application Curves
Figure 10-2 is the scope shot showing the switch getting toggled from close to open at time a). Before toggling, the voltage at VIN0 stays low at roughly 2.7 V. Once the switch opens, the voltage at VIN0 gets pulled high to the VS voltage. The INT pin is asserted shortly after the switch toggles at time b) to notify the microcontroller a switch state change event has occurred.
Figure 10-2 Measured Waveform Showing VIN0 Pin and INT Pin Voltages