ZHCSGQ0A September 2017 – February 2022 TIC10024-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VS Pin
- 8.3.2 VDD Pin
- 8.3.3 Device Initialization
- 8.3.4 Device Trigger
- 8.3.5 Device Reset
- 8.3.6 VS Under-Voltage (UV) Condition
- 8.3.7 VS Over-Voltage (OV) Condition
- 8.3.8 Switch Inputs Settings
- 8.3.9 Interrupt Generation and INT Assertion
- 8.3.10 Temperature Monitor
- 8.3.11 Parity Check And Parity Generation
- 8.3.12 Cyclic Redundancy Check (CRC)
- 8.4 Device Functional Modes
- 9 Programming
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
8.3.9 Interrupt Generation and INT Assertion
The INT pin is an active-low, open-drain output that asserts low when an event (switch input state change, temperature warning, over-voltage shut down etc.) is detected by the TIC10024-Q1. An external pull-up resistor to VDD is needed on the INT pin (see Figure 8-4). The INT pin can also be connected directly to a 12-V automotive battery to support the microcontroller wake-up feature, as describe in Section 8.3.9.3.
Figure 8-4 INT Connection Example #1