4 Revision History
Changes from Revision * (April 2021) to Revision A (September 2023)
- 通篇更正了拼寫錯誤和格式小問題Go
- Fixed spelling errors throughout the documentGo
- Updated I2C pull-up Resistor RecommendationsGo
- Updated Legend for Pin Functions TableGo
- Removed the tCLK-MISS specification from the CSI-2 Timing
Specifications tableGo
- Removed obstructions in CSI-2 General Frame Format figure to make text clearerGo
- Clarified the clock speed and the configuration settings of
non-synchronous clock mode Go
- Added clarification that MODE pin option 0 straps the device to CSI-2 Non-Synchronous back channel and
MODE pin option 4 straps the device to CSI-2 Synchronous back channelGo
- Changed I2C terminology to "Controller" and
"Target"Go
- Updated the transmission channel requirements for Coaxial and
STP/STQ Cable ApplicationsGo
- Fixed spelling errors throughout the documentGo
- Fixed spelling errors throughout
the documentGo
- Removed mention of
older siliconGo
- Changed "VC ID" to "VC-ID"Go
- Changed "VC ID" to "VC-ID"Go
- Changed "VC ID" to "VC-ID"Go
- Clarified that CSI-2 forwarding should be disabled before CSI-2
replicate mode is enabledGo
- Changed I2C terminology to "Controller" and "Target"Go
- Added a sentence to clarify that VI2C must match the voltage
applied to VDDIOGo
- Reworded the Serial Control Bus section to reference VI2C instead
of VDDIOGo
- Changed I2C terminology to "Controller" and
"Target"Go
- Added register addresses for the RX Port ID registersGo
- Fixed spelling errors throughout the documentGo
- Changed I2C terminology to "Controller" and "Target"Go
- Removed information suggesting that the Rx Port intended for messaging must always be selected with Register 0x4C when communicating with a remote target deviceGo
- Changed I2C terminology to "Controller" and "Target"Go
- Corrected the total number of TargetID and TargetAlias pairs of registers for the
deviceGo
- Clarified that the write enable bit in register 0x4C needs to be set before
configuring remote target addressesGo
- Added additional information about how to configure a broadcast
write to remote devicesGo
- Changed I2C terminology to "Controller" and "Target"Go
- Changed I2C terminology to "Controller" and
"Target"Go
- Updated the I2C Controller Proxy description Go
- Changed I2C terminology to "Controller" and "Target"Go
- Fixed register address errors in the Typical I2C Timing Register Settings tableGo
- Removed details about the internal reference clockGo
- Fixed spelling errors throughout the documentGo
- Changed I2C terminology to "Controller" and
"Target"Go
- Clarified instructions for how to configure Pattern Generation on the CSI-2 PortsGo
- Fixed spelling errors throughout the documentGo
- Fixed spelling errors throughout the documentGo
- Fixed spelling errors throughout the documentGo
- Changed I2C terminology to "Controller" and "Target"Go
- Removed all RESERVED registers from the datasheetGo
- Made register bits 0x34[5:4] public and updated the description of register bit 0x34[1]Go
- Corrected a bit description typo for bit 4 of register 0x4AGo
- Updated description of register 0x4E[1] to clarify
functionalityGo
- Updated the description sections of registers 0x51-0x54Go
- Fixed typos in the description for registers 0x90-0x9FGo
- Removed RESERVED indirect register pages in the description of register bits
0xB0[5:2]Go
- Made register 0xB6 publicGo
- Updated the bit description of 0xB9[3:0]Go
- Updated the name of Indirect Register Page 0 to PATGEN_AND_CSI-2Go
- Updated the PoC descriptionGo
- Updated both typical connection diagrams to include a reference to App Note
SLVA689Go
- Added clarification for the recommended ferrite bead characteristics on the power supply railsGo
- Removed optional 10 kΩ pulldown resistor on Pin 4 in the Typical Connection DiagramGo
- Fixed part number typo in the Power-Up Sequencing With Non-Synchronous
Clocking Mode figure Go
- Updated MIPI CSI-2 D-PHY layout recommendationsGo