ZHCSNJ8A April 2021 – September 2023 TDES960
PRODUCTION DATA
The V3Link BIST is configured and enabled by programming the BIST Control register. Set 0xB3 = 0x01 to enable BIST and set 0xB3 = 00 to disable BIST. BIST pass or fail status may be brought to GPIO pins by selecting the Pass indication for each receive port using the GPIOx_PIN_CTL registers. The Pass/Fail status will be de-asserted low for each data error detected on the selected port input data. In addition, it is advisable to bring the Receiver Lock status for selected ports to the GPIO pins as well. After completion of BIST, the BIST Error Counter may be read to determine if errors occurred during the test. If the TDES960 failed to lock to the input signal or lost lock to the input signal, the BIST Error Counter will indicate 0xFF. The maximum normal count value will be 0xFE.
During BIST, TDES960 output activity are gated by BIST_Control[7:6] (BIST_OUT_MODE[1:0]) as follows:
00 : Outputs disabled during BIST
10 : Outputs enabled during BIST
When enabling the outputs by setting BIST_OUT_MODE = 10, the CSI-2 will be inactive by default (LP11 state). To exercise the CSI-2 interface during BIST mode, it is possible to Enable Pattern Generator to send a video data pattern on the CSI-2 outputs.
The BIST clock frequency is controlled by the BIST_CLOCK_SOURCE field in the BIST Control register. This 2-bit value will be written to the Serializer register 0x14[2:1]. A value of 00 will select an external clock. A non-zero value will enable an internal clock of the frequency defined in the Serializer register 0x14. Note that when the TDES960 is paired with a DVP Mode serializer, a setting of 11 may result in a frequency that is too slow for the TDES960 to recover. The BIST_CLOCK_SOURCE field is sampled at the start of BIST. Changing this value after BIST is enabled will not change operation.