ZHCSNJ8A April 2021 – September 2023 TDES960
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 DC Electrical Characteristics
- 6.6 AC Electrical Characteristics
- 6.7 CSI-2 Timing Specifications
- 6.8 Recommended Timing for the Serial Control Bus
- 6.9 Timing Diagrams
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4
Device Functional Modes
- 7.4.1 CSI-2 Mode
- 7.4.2 RAW Mode
- 7.4.3 MODE Pin
- 7.4.4 REFCLK
- 7.4.5 Receiver Port Control
- 7.4.6 Input Jitter Tolerance
- 7.4.7 Adaptive Equalizer
- 7.4.8 Channel Monitor Loop-Through Output Driver
- 7.4.9 RX Port Status
- 7.4.10 Sensor Status
- 7.4.11 GPIO Support
- 7.4.12 RAW Mode LV / FV Controls
- 7.4.13 CSI-2 Protocol Layer
- 7.4.14 CSI-2 Short Packet
- 7.4.15 CSI-2 Long Packet
- 7.4.16 CSI-2 Data Identifier
- 7.4.17 Virtual Channel and Context
- 7.4.18 CSI-2 Mode Virtual Channel Mapping
- 7.4.19 CSI-2 Transmitter Frequency
- 7.4.20 CSI-2 Output Bandwidth
- 7.4.21 CSI-2 Transmitter Status
- 7.4.22 Video Buffers
- 7.4.23 CSI-2 Line Count and Line Length
- 7.4.24 FrameSync Operation
- 7.4.25
CSI-2 Forwarding
- 7.4.25.1 Best-Effort Round Robin CSI-2 Forwarding
- 7.4.25.2 Synchronized CSI-2 Forwarding
- 7.4.25.3 Basic Synchronized CSI-2 Forwarding
- 7.4.25.4 Line-Interleaved CSI-2 Forwarding
- 7.4.25.5 Line-Concatenated CSI-2 Forwarding
- 7.4.25.6 CSI-2 Replicate Mode
- 7.4.25.7 CSI-2 Transmitter Output Control
- 7.4.25.8 Enabling and Disabling CSI-2 Transmitters
- 7.5
Programming
- 7.5.1 Serial Control Bus
- 7.5.2 Second I2C Port
- 7.5.3 I2C Target Operation
- 7.5.4 Remote Target Operation
- 7.5.5 Remote Target Addressing
- 7.5.6 Broadcast Write to Remote Devices
- 7.5.7 I2C Controller Proxy
- 7.5.8 I2C Controller Proxy Timing
- 7.5.9 Interrupt Support
- 7.5.10 Error Handling
- 7.5.11 Timestamp – Video Skew Detection
- 7.5.12 Pattern Generation
- 7.5.13 V3Link BIST Mode
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTD|64
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTD|64
訂購信息
7.4.8 Channel Monitor Loop-Through Output Driver
The TDES960 includes an internal Channel Monitor Loop-through output on the CMLOUTP/N pins. The CMLOUTP/N pins supply a buffered loop-through output driver to observe the jitter after equalization for each of the four RX receiver channels. The CMLOUT monitors the post EQ stage, thus providing the recovered input of the deserializer signal. The measured serial data width on the CMLOUT loop-through is the total jitter including the internal driver, AEQ, back channel echo, and so forth. Each channel also has its own CMLOUT monitor and can be used for debug purposes. This CMLOUT is useful in identifying gross signal conditioning issues.
3 shows the minimum CMLOUT differential eye opening as a measure of acceptable forward channel signal integrity. A CMLOUT eye opening of at least 0.35 UI suggests that the forward channel signal integrity is likely acceptable. However, further testing such as BIST is recommended to verify error-free operation. An eye opening of less than 0.35 UI indicates possible issues with the forward channel signal integrity.
| PARAMETER | TEST CONDITIONS | PIN | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|---|
| EW | Differential Output Eye Opening | RL = 100 Ω (Figure 7-4) | CMLOUTP, CMLOUTN | 0.35 | UI(1) | ||||
CSI-2 Mode, Serializer Synchronous Mode: 1 UI = 1 / ( 160 x REFCLK ) (typ)
CSI-2 Mode, Serializer Non-synchronous Mode: 1 UI = 1 / ( 80 x CLK_IN) (typ)
RAW 10-bit mode: 1 UI = 1 / ( 28 x PCLK / 2 )
RAW 12-bit HF mode: 1 UI = 1 / ( 28 x 2/3 x PCLK )
RAW 12-bit LF mode: 1 UI = 1 / ( 28 x PCLK )
Figure 7-4 CMLOUT Output DriverTable 7-8 includes details on selecting the corresponding RX receiver of CMLOUTP/N configuration.
| V3LINK RX Port 0 | V3LINK RX Port 1 | V3LINK RX Port 2 | V3LINK RX Port 3 | |
|---|---|---|---|---|
| ENABLE MAIN LOOPTHRU DRIVER | 0xB0 = 0x14 0xB1 = 0x00 0xB2 = 0x80 | 0xB0 = 0x14 0xB1 = 0x00 0xB2 = 0x80 | 0xB0 = 0x14 0xB1 = 0x00 0xB2 = 0x80 | 0xB0 = 0x14 0xB1 = 0x00 0xB2 = 0x80 |
| SELECT CHANNEL MUX | 0xB1 = 0x01 0xB2 = 0x01 | 0xB1 = 0x01 0xB2 = 0x02 | 0xB1 = 0x01 0xB2 = 0x04 | 0xB1 = 0x01 0xB2 = 0x08 |
| SELECT RX PORT | 0xB0 = 0x04 0xB1 = 0x0F 0xB2 = 0x01 0xB1 = 0x10 0xB2 = 0x02 | 0xB0 = 0x08 0xB1 = 0x0F 0xB2 = 0x01 0xB1 = 0x10 0xB2 = 0x02 | 0xB0 = 0x0C 0xB1 = 0x0F 0xB2 = 0x01 0xB1 = 0x10 0xB2 = 0x02 | 0xB0 = 0x10 0xB1 = 0x0F 0xB2 = 0x01 0xB1 = 0x10 0xB2 = 0x02 |