ZHCSNJ8A April 2021 – September 2023 TDES960
PRODUCTION DATA
The V3Link receiver checks the decoded data parity to detect any errors in the received V3Link frame. Parity errors are counted up and accessible through the RX_PAR_ERR_HI and RX_PAR_ERR_LO registers 0x55 and 0x56 to provide combined 16-bit error counter. In addition, a parity error flag can be set once a programmed number of parity errors have been detected. This condition is indicated by the PARITY_ERROR flag in the RX_PORT_STS1 register. Reading the counter value will clear the counter value and PARITY_ERROR flag. An interrupt may also be generated based on assertion of the parity error flag. By default, the parity error counter will be cleared and flag will be cleared on loss of Receiver lock. To ensure an exact read of the parity error counter, parity checking must be disabled in the GENERAL_CFG register 0x02 before reading the counter.