ZHCSNJ8A April 2021 – September 2023 TDES960
PRODUCTION DATA
The proxy controller timing parameters are based on the REFCLK timing. Timing accuracy for the I2C proxy controller based on the REFCLK clock source attached to the TDES960 deserializer. The I2C Controller regenerates the I2C read or write access using timing controls in the registers 0xA and 0xB to regenerate the clock and data signals to meet the desired I2C timing in Standard, Fast, or Fast-mode Plus modes of operation.
I2C Controller SCL High Time is set in register 0xA[7:0]. This field configures the high pulse width of the SCL output when the Serializer is the Controller on the local deserializer I2C bus. The default value is set to provide a minimum 5-μs SCL high time with the reference clock at 25 MHz + 100 ppm including four additional oscillator clock periods or synchronization and response time. Units are 40 ns for the nominal oscillator clock frequency, giving Min_delay = 40 ns × (SCL_HIGH_TIME + 4).
I2C Controller SCL Low Time is set in register 0xB[7:0]. This field configures the low pulse width of the SCL output when the Serializer is the Controller on the local deserializer I2C bus. This value is also used as the SDA setup time by the I2C Target for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. The default value is set to provide a minimum 5-μs SCL high time with the reference clock at 25 MHz + 100ppm including four additional oscillator clock periods or synchronization and response time. Units are 40 ns for the nominal oscillator clock frequency, giving Min_delay = 40 ns × (SCL_HIGH_TIME + 4). See Table 7-18 example settings for Standard mode, Fast mode and Fast-mode Plus timing.
| I2C MODE | SCL HIGH TIME | SCL LOW TIME | ||
|---|---|---|---|---|
| 0xA[7:0] | NOMINAL DELAY AT REFCLK = 25 MHz | 0xB[7:0] | NOMINAL DELAY AT REFCLK = 25 MHz | |
| Standard | 0x7A | 5.04 μs | 0x7A | 5.04 μs |
| Fast | 0x13 | 0.920 μs | 0x25 | 1.64 μs |
| Fast - Plus | 0x06 | 0.400 μs | 0x0C | 0.640 μs |