ZHCSCB3D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
This mode is mainly used for systems driving TDM ports or systems where the MCK is not related to the audio sampling rate. For example, where the audio ADC must share a clock source with the central processor (commonly, 12 MHz, 24 MHz, or 27 MHz.)
Under these conditions, set automatic configuration register CLKDET_EN (Page 0, 0x20) to 0, and manually configure the PLL using registers (Page 0, 0x28 - 0x2D); see Software-Controlled Devices Manual PLL Calculation. The clock tree must also be set to use the PLL output as the master mode SCKOUT source, and have the appropriate SCK-to-BCK and BCK-to-LRCK dividers set.