ZHCSCB3D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
| CONDITIONS | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| fSCL | SCL clock frequency | Standard | 100 | kHz | |
| Fast | 400 | kHz | |||
| tBUF | Bus free time between a STOP and START condition | Standard | 4.7 | µs | |
| Fast | 1.3 | ||||
| tLOW | Low period of the SCL clock | Standard | 4.7 | µs | |
| Fast | 1.3 | ||||
| tHI | High period of the SCL clock | Standard | 4.0 | µs | |
| Fast | 600 | ns | |||
| tRS-SU | Setup time for repeated START condition | Standard | 4.7 | µs | |
| Fast | 600 | ns | |||
| tS-HD | Hold time for START condition | Standard | 4.0 | µs | |
| Fast | 600 | ns | |||
| tRS-HD | Hold time for repeated START condition | Standard | 4.0 | µs | |
| Fast | 600 | ns | |||
| tD-SU | Data setup time | Standard | 250 | ns | |
| Fast | 100 | ||||
| tD-HD | Data hold time | Standard | 0 | 900 | ns |
| Fast | 0 | 900 | |||
| tSCL-R | Rise time of SCL signal | Standard | 20 + 0.1CB | 1000 | ns |
| Fast | 20 + 0.1CB | 300 | |||
| tSCL-R1 | Rise time of SCL signal after a repeated START condition and after an acknowledge bit | Standard | 20 + 0.1CB | 1000 | ns |
| Fast | 20 + 0.1CB | 300 | |||
| tSCL-F | Fall time of SCL signal | Standard | 20 + 0.1CB | 1000 | ns |
| Fast | 20 + 0.1CB | 300 | |||
| tSDA-R | Rise time of SDA signal | Standard | 20 + 0.1CB | 1000 | ns |
| Fast | 20 + 0.1CB | 300 | |||
| tSDA-F | Fall time of SDA signal | Standard | 20 + 0.1CB | 1000 | ns |
| Fast | 20 + 0.1CB | 300 | |||
| tP-SU | Setup time for STOP condition | Standard | 4.0 | µs | |
| Fast | 600 | ns | |||
| CB | Capacitive load for SDA and SCL line | 400 | pF | ||
| tSP | Pulse duration of spike suppressed | Fast | 50 | ns | |
| VNH | Noise margin at high level for each connected device (including hysteresis) | 0.2VDD | V | ||
Figure 1. I2C Control Interface Timing