ZHCSCB3D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
The PCM186x family of audio, analog-to-digital converters (ADCs) features a highly flexible, audio front end that supports input levels from small millivolt microphone inputs to 2.1-VRMS line inputs. The analog front end can be configured to support either differential or single-ended inputs, providing optimal performance when using differential inputs. Mixing single-ended and differential inputs is possible. A digital microphone interface is available in the software-controlled devices.
These devices support advanced clocking with the aid of an integrated oscillator circuit and an on-chip analog phase-locked loop (PLL). The integrated oscillator circuit allows for the use of an external crystal or an external master clock as the clock source in master mode. In addition, the PLL can be used to generate an on-chip master clock that can be shared with the rest of the system, all from a bit clock input. This feature is useful in systems where the audio source has no master clock to drive digital-to-analog converters (DACs) and amplifiers. The on-chip clock monitoring system can also be monitored by the system microcontroller, in case clocks are lost and the device enters sleep or standby state.
The secondary analog-to-digital converter (ADC) is a low-power, non-audio ADC that is used in sleep mode to monitor the analog inputs. The secondary ADC is also used in controlsense mode to measure dc voltages in a system, such as battery voltage and control potentiometers. In addition, controlsense features offer an option to generate interrupts after detected voltages cross specific thresholds, allowing the microcontroller to be in a lower-power sleep mode while the control voltages being measured are stable.
Control registers in this data sheet are shown as REGISTER_BIT_or_BYTE_NAME (page.x hex_address).