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ZHCSCB3D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DBT|30
- MPDS019J

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

9.3.9.4.2 Clock Sources for Software-Controlled Devices

The PCM1862, PCM1863, PCM1864, and PCM1865 software-controlled devices support a wide range of options for generating the clocks required to operate the ADC section, as well as an interface and other control blocks, as shown in Figure 34.

The clocks for the PLL require a source reference clock. This clock source can be configured on software devices as the XTAL, SCK or BCK.

These software-controlled devices share a similar clock tree for the generation and distribution of clocks, as shown in Figure 33.

Register CLK_MODE (Page.0 0x20) is used to configure the clock configuration. Bits [5:7] configure the OR and MUX for the incoming MCLK.

Register MST_MODE (Page.0 0x20) is used to set the device in master or slave mode. Bits [1:3] set clock sources for the ADC, DSP1 and DSP2. These can mostly be ignored for the most common applications, but are provided for advanced users.

Register MST_SCK_SRC (Page.0 0x20) is used to set the source of the SCKO in master mode. The master mode BCK and LRCK will be a division of this. The selection is either SCKI/XTI or PLL. PLL can be used when you have a non-audio rate reference clock (BCK or SCKI), as well as when you have an SCKI that is much too slow for what is required for SCKO.

Most applications will use XTI/SCKI as the source for master mode SCK.

The CLKDET_EN (Page.0, 0x20) register bit (auto clock detector) is important; the clock detector is mainly functional for slave modes, and for master modes where the master clock is a 256×, 384×, or 512× multiple of the incoming data rate.

The relation between the master mode configuration registers is shown in Table 7.

NOTE

Non audio related master clock sources can be used with the PCM186x software -controlled devices providing the PLL is programmed manually. CLKDET_EN should be set to 0.

The result of configurations can be checked by reading registers FS_INFO / CURRENT_BCK_RATIO (Page.0 0x73 and 0x74).

NOTE

In master mode on software-controlled devices, only the following BCK to LRCK ratios are supported: 32x, 48x, 64x and 256x. 128x is not supported

Table 7. Master Mode Clock Configuration Registers

CLOCK MULTIPLEXER	FUNCTION	BITS
MST_SCK_SRC	Master mode SCK source	Page 0, register 0x20, bits[5]
DIVIDER	FUNCTION	BITS
CLK_DIV_PLL_SCK	Clock divider of PLL to SCKOUT divider (for example, master mode or BCK PLL slave mode with SCK for the rest of the system)	Pg0, reg 0x25, bits[0:6]
CLK_DIV_SCK_BCK	Ratio of master clock (SCK) to bit clock (BCK)	Pg0, reg 0x26, bits[0:6]
CLK_DIV_BCK_LRCK	Ratio of bit clock (BCK) to left-right clock (LRCK)	Pg0, reg 0x27, bits[0:6]

PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865 PCM186x-clock-tree.gif

Figure 34. PLL Clock Source and Clock Distribution