SNVSB23 March 2018 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1
PRODUCTION DATA.
Address: 0x21
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Reserved | Reserved | SYNC_CLK
_MASK |
Reserved | TDIE_WARN
_MASK |
Reserved | I_LOAD_
READY_MASK |
|
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7 | Reserved | R/W | 1h | |
| 6:5 | Reserved | R/W | 0h | |
| 4 | SYNC_CLK_MASK | R/W | X | Masking for the external clock detection interrupt (the NO_SYNC_CLK bit in the INT_TOP1 register)
0h = Interrupt generated 1h = Interrupt not generated |
| 3 | Reserved | R/W | 0h | |
| 2 | TDIE_WARN_MASK | R/W | X | Masking for the thermal warning interrupt (the TDIE_WARN bit in the INT_TOP1 register)
This bit does not affect TDIE_WARN_STAT status bit in the TOP_STAT register. 0h = Interrupt generated 1h = Interrupt not generated |
| 1 | Reserved | R/W | 0 | |
| 0 | I_LOAD_READY_MASK | R/W | X | Masking for the load-current measurement-ready interrupt (the I_LOAD_READY bit in the INT_TOP register).
0h = Interrupt generated 1h = Interrupt not generated |