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SNVSB23 March 2018 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1

PRODUCTION DATA.

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

RNF|26

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

8.3.7 Diagnosis and Protection Features

The LP8752x-Q1 is capable of providing four levels of protection features:

Information of valid regulator output voltage, which sets interrupt or PGOOD signal;
Warnings for diagnosis, which set interrupt;
Protection events that are disabling the regulators affected; and
Faults that are causing the device to shut down.

The LP8752x-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared.

When a fault is detected, it is indicated by a RESET_REG interrupt flag (in INT2_TOP register) after next start-up.

Table 5. Summary of Interrupt Signals

EVENT	RESULT	INTERRUPT REGISTER AND BIT	INTERRUPT MASK	STATUS BIT	RECOVERY/INTERRUPT CLEAR
Current limit triggered (20-µs debounce)	Interrupt	INT_BUCKx = 1 BUCKx_ILIM_INT = 1	BUCKx_ILIM_MASK	BUCKx_ILIM_STAT	Write 1 to BUCKx_ILIM_INT bit Interrupt is not cleared if current limit is active.
Short circuit (V_VOUT < 0.35 V at 1 ms after enable) or overload (V_VOUT decreasing below 0.35 V during operation, 1 ms debounce)	Regulator disable and interrupt	INT_BUCKx = 1 BUCKx_SC_INT = 1	N/A	N/A	Write 1 to BUCKx_SC_INT bit
Thermal warning	Interrupt	TDIE_WARN = 1	TDIE_WARN_MASK	TDIE_WARN_STAT	Write 1 to TDIE_WARN bit Interrupt is not cleared if temperature is above thermal warning level.
Thermal whutdown	All regulators disabled and Output GPIOx set to low and interrupt.	TDIE_SD = 1	N/A	TDIE_SD_STAT	Write 1 to TDIE_SD bit Interrupt is not cleared if temperature is above thermal shutdown level.
VANA overvoltage (VANA_OVP)	All regulators disabled and Output GPIOx set to low and interrupt.	INT_OVP	N/A	OVP_STAT	Write 1 to INT_OVP bit Interrupt is not cleared if VANA voltage is above VANA OVP level.
Power Good, output voltage reaches the programmed value	Interrupt	INT_BUCKx = 1 BUCKx_PG_INT = 1	BUCKx_PG_MASK	BUCKx_PG_STAT	Write 1 to BUCKx_PG_INT bit
GPIO	Interrupt	INT_GPIO	GPIO_MASK	GPIO_IN register	Write 1 to INT_GPIO bit
External clock appears or disappears	Interrupt	NO_SYNC_CLK⁽¹⁾	SYNC_CLK_MASK	SYNC_CLK_STAT	Write 1 to NO_SYNC_CLK bit
Load current measurement ready	Interrupt	I_LOAD_READY = 1	I_LOAD_READY_MASK	N/A	Write 1 to I_LOAD_READY bit
Start-up (NRST rising edge)	Device ready for operation; registers reset to default values and interrupt.	RESET_REG = 1	RESET_REG_MASK	N/A	Write 1 to RESET_REG bit
Glitch on supply voltage and UVLO triggered (VANA falling and rising)	Immediate shutdown followed by power up; registers reset to default values and interrupt.	RESET_REG = 1	RESET_REG_MASK	N/A	Write 1 to RESET_REG bit
Software requested reset	Immediate shutdown followed by power up; registers reset to default values and interrupt.	RESET_REG = 1	RESET_REG_MASK	N/A	Write 1 to RESET_REG bit

(1) Interrupt is generated during clock detector operation, and in cases where clock is not available when clock detector is enabled.