SNVSB23 March 2018 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1
PRODUCTION DATA.
Address: 0x14
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| BUCK2_SHUTDOWN_DELAY[3:0] | BUCK2_STARTUP_DELAY[3:0] |
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7:4 | BUCK2_SHUTDOWN_DELAY[3:0] | R/W | X | Shutdown delay of the BUCK2 regulator from the falling edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table.
0h = 0 ms 1h = 1 ms ... Fh = 15 ms (Default from OTP memory) |
| 3:0 | BUCK2_STARTUP_DELAY[3:0] | R/W | X | start-up delay of the BUCK2 regulator from the rising edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table.
0h = 0 ms 1h = 1 ms Fh = 15 ms |