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ZHCSK16A October 2017 – July 2019 LMK04228

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

NKD|64
- MPQS032C

散熱焊盤機械數據 (封裝 | 引腳)

NKD|64
- QFND765

訂購信息

zhcsk16a_oa

9.3.1 SYNC/SYSREF

The SYNC and SYSREF signals share the same clocking path. To properly use SYNC and SYSREF for JESD204B, it is important to understand the SYNC/SYSREF system. Figure 5 illustrates the detailed diagram of a clock output block with SYNC circuitry included. Figure 6 illustrates the interconnects and highlights some important registers used in controlling the device for SYNC/SYSREF purposes.

To reset or synchronize a divider, the following conditions must be met:

SYNC_EN must be set. This ensures proper operation of the SYNC circuitry.
SYSREF_MUX and SYNC_MODE must be set to a proper combination to provide a valid SYNC/SYSREF signal.
- If SYSREF block is being used, the SYSREF_PD bit must be clear.
- If the SYSREF Pulser is being used, the SYSREF_PLSR_PD bit must be clear.
For each SDCLKoutY being used for SYSREF, respective SDCLKoutY_PD bits must be cleared.
SYSREF_DDLY_PD and DCLKoutX_DDLY_PD bits must be clear to power up the digital delay circuitry during SYNC as use requires.
The SYNC_DISX bit must be clear to allow SYNC/SYSREF signal to divider circuit. The SYSREF_MUX register selects the SYNC source which resets the SYSREF/CLKoutX dividers provided the corresponding SYNC_DISX bit is clear.
Other bits which impact the operation of SYNC such as SYNC_1SHOT_EN may be set as desired.

Table 2 illustrates the some possible combinations of SYSREF_MUX and SYNC_MODE.

Table 2. Some Possible SYNC Configurations

NAME	SYNC_MODE	SYSREF_MUX	OTHER	DESCRIPTION
SYNC Disabled	0	0	CLKin0_OUT_MUX ≠ 0	No SYNC will occur.
Pin or SPI SYNC	1	0	CLKin0_OUT_MUX ≠ 0	Basic SYNC functionality, SYNC pin polarity is selected by SYNC_POL. To achieve SYNC through SPI, toggle the SYNC_POL bit.
Differential input SYNC	0 or 1	0 or 1	CLKin0_OUT_MUX = 0	Differential CLKin0 now operates as SYNC input.
JESD204B Pulser on pin transition.	2	2	SYSREF_PULSE_CNT sets pulse count	Produce SYSREF_PULSE_CNT programmed number of pulses on pin transition. SYNC_POL can be used to cause SYNC through SPI.
JESD204B Pulser on SPI programming.	3	2	SYSREF_PULSE_CNT sets pulse count	Programming SYSREF_PULSE_CNT register starts sending the number of pulses.
Re-clocked SYNC	1	1	SYSREF operational, SYSREF Divider as required for training frame size.	Allows precise SYNC for n-bit frame training patterns for non-JESD converters such as LM97600.
External SYSREF request	0	2	SYSREF_REQ_EN = 1 Pulser powered up	When SYNC pin is asserted, continuous SYSERF pulses occur. Turning on and off of the pulses is synchronized to prevent runt pulses from occurring on SYSREF.
Continuous SYSREF	X	3	SYSREF_PD = 0 SYSREF_DDLY_PD = 0 SYSREF_PLSR_PD = 1 ⁽¹⁾	Continuous SYSREF signal.
Direct SYSREF distribution	0	0	CLKin0_OUT_MUX = 0 SDCLKoutY_DDLY = 0 (Local sysref DDLY bypassed) SYSREF_DDLY_PD = 1 SYSREF_PLSR_PD = 1 SYSREF_PD = 1.	A direct fan-out of SYSREF with no reclocking to clock distribution path.

(1) SDCLKoutY_PD = 0 as required per SYSREF output. This applies to any SYNC or SYSREF output on SDCLKoutY when SDCLKoutY_MUX = 1 (SYSREF output)