6 Pin Configuration and Functions

Figure 6-1 RTV Package32-Pin QFN(Top View)

Table 6-1 Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
HIGH-SPEED DIFFERENTIAL I/OS
SDI_IO+	1	I/O, Analog	Single-ended complementary inputs or outputs with on-chip 75-? termination at SDI_IO+ and SDI_IO–. SDI_IO± include integrated return loss networks designed to meet the SMPTE input and output return loss requirements. Connect SDI_IO+ to a BNC through a 4.7-μF, AC-coupling capacitor. SDI_IO– should be similarly AC-coupled and terminated with an external 4.7-μF capacitor and 75-Ω resistor to GND. EQ mode: SDI_IO+ is the 75-Ω input port of the adaptive cable equalizer for SMPTE video applications. CD mode: SDI_IO+ is the 75-Ω output port of the cable driver for SMPTE video applications.
SDI_IO–	2	I/O, Analog
SDI_OUT–	7	O, Analog	Single-ended complementary outputs with on-chip 75-? termination at SDI_OUT+ and SDI_OUT–. SDI_OUT± include integrated return loss networks designed to meet the SMPTE output return loss requirements. SDI_OUT± is used as a second cable driver. Connect SDI_OUT+ to a BNC through a 4.7-μF, AC-coupling capacitor. SDI_OUT– should be similarly AC-coupled and terminated with an external 4.7-μF capacitor and 75-Ω resistor to GND. EQ mode: SDI_OUT± can be enabled as a loop-through 75-Ω output port. It outputs the reclocked data from the adaptive cable equalizer to form a loop-through output with adaptive cable equalizer, reclocker, and cable driver. CD mode: SDI_OUT± is the second 75-Ω fan-out cable driver.
SDI_OUT+	8	O, Analog
IN0–	18	I, Analog	Differential inputs from host video processor. On-chip 100-? differential termination. Requires external 4.7-μF, AC-coupling capacitors for SMPTE applications.
IN0+	19	I, Analog
OUT0–	22	O, Analog	Differential outputs to host video processor. On-chip 100-? differential termination. Requires external 4.7-μF, AC-coupling capacitors for SMPTE applications.
OUT0+	23	O, Analog
CONTROL PINS
OUT0_SEL	4	I, LVCMOS	OUT0_SEL enables the use of the 100-? host-side output driver at OUT0±. See Table 8-3 for details. OUT0_SEL is internally pulled high by default (OUT0 disabled).
EQ/CD_SEL	5	I, LVCMOS	EQ/CD_SEL selects the signal direction of the LMH1297 bidirectional I/O. It configures the LMH1297 as an adaptive equalizer (EQ mode) or as a cable driver (CD mode). See Table 8-2 for details. EQ/CD_SEL is internally pulled low by default (EQ mode).
HOST_EQ0	9	I, 4-LEVEL	HOST_EQ0 selects the driver output amplitude and de-emphasis level for OUT0± (in EQ mode) and equalizer setting for IN0± (in CD mode). See Table 8-5 and Table 8-10 for details.
MODE_SEL	12	I, 4-LEVEL	MODE_SEL enables the SPI or SMBus serial control interface. See Table 8-11 for details.
SDI_OUT_SEL	14	I, LVCMOS	SDI_OUT_SEL enables the use of the 75-? output driver at SDI_OUT±. See Table 8-3 for details. SDI_OUT_SEL is internally pulled high by default (SDI_OUT disabled).
OUT_CTRL	17	I, 4-LEVEL	OUT_CTRL selects the signal being routed to the output. It is used to enable or bypass the reclocker and to enable or bypass the cable equalizer. See Table 8-7 for details.
SDI_VOD	24	I, 4-LEVEL	SDI_VOD selects one of four output amplitudes for the cable drivers at SDI_IO± and SDI_OUT±. See Table 8-8 for details.
LOCK_N	27	O, LVCMOS, OD	LOCK_N is the reclocker lock indicator. LOCK_N is pulled low when the reclocker has acquired lock condition. LOCK_N is a 3.3-V tolerant, open-drain output. It requires an external resistor to a logic supply. LOCK_N can be reconfigured to indicate Carrier Detector (CD_N) or Interrupt (INT_N) through register programming. See Section 8.3.10.
ENABLE	32	I, LVCMOS	A logic-high at ENABLE enables normal operation for the LMH1297. A logic-low at ENABLE places the LMH1297 in Power-Down mode. ENABLE is internally pulled high by default.
SPI SERIAL CONTROL INTERFACE, MODE_SEL = F (FLOAT)
SS_N	11	I, LVCMOS	SS_N is the Target Select. When SS_N is at logic Low, it enables SPI access to the LMH1297 target device. SS_N is a 2.5-V LVCMOS input and is internally pulled high by default.
MOSI	13	I, LVCMOS	MOSI is the SPI serial control data input to the LMH1297 target device when the SPI bus is enabled. MOSI is a 2.5-V LVCMOS input. An external pullup resistor is recommended.
MISO	28	O, LVCMOS	MISO is the SPI serial control data output from the LMH1297 target device. MISO is a 2.5-V LVCMOS output.
SCK	29	I, LVCMOS	SCK is the SPI serial input clock to the LMH1297 target device when the SPI interface is enabled. SCK is a 2.5-V LVCMOS input. An external pullup resistor is recommended.
SMBUS SERIAL CONTROL INTERFACE, MODE_SEL = L (1 KΩ TO VSS)
ADDR0	11	Strap, 4-LEVEL	ADDR[1:0] are 4-level straps, read into the device at power up. They are used to select one of the 16 supported SMBus addresses when SMBus is enabled. See Table 8-12 for details.
SDA	13	I/O, LVCMOS, OD	SDA is the SMBus bidirectional data line to or from the LMH1297 target device when SMBus is enabled. SDA is an open-drain I/O and requires an external pullup resistor to the SMBus termination voltage. SDA is 3.3-V tolerant.
ADDR1	28	Strap, 4-LEVEL	ADDR[1:0] are 4-level straps, read into the device at power up. They are used to select one of the 16 supported SMBus addresses when SMBus is enabled. See Table 8-12 for details.
SCL	29	I/O, LVCMOS, OD	SCL is the SMBus input clock to the LMH1297 target device when SMBus is enabled. It is driven by a LVCMOS open-drain driver from the SMBus controller. SCL requires an external pullup resistor to the SMBus termination voltage. SCL is 3.3-V tolerant.
RESERVED
RSV1 RSV2 RSV3 RSV4 RSV5	10 15 16 25 26	—	Reserved pins. Do not connect.
POWER
VSS	3, 6, 20	I, Ground	Ground reference.
VDD_CDR	21	I, Power	VDD_CDR powers the reclocker circuitry. It is connected to the same 2.5-V ± 5% supply as VIN.
VIN	30	I, Power	VIN is connected to an external 2.5-V ± 5% power supply.
VDD_LDO	31	O, Power	VDD_LDO is the output of the internal 1.8-V LDO regulator. VDD_LDO output requires an external 1-μF and 0.1-μF bypass capacitor to VSS. The internal LDO is designed to power internal circuitry only.
EP	—	I, Ground	EP is the exposed pad at the bottom of the RTV package. The exposed pad should be connected to the VSS plane through a 3 × 3 via array.

(1) I = input, O = output, I/O = input or output, OD = open drain, LVCMOS = 2-state logic, 4-LEVEL = 4-state logic