ZHCSK26E March 2017 – July 2022 LMH1297
PRODUCTION DATA
For general LMH1297 design requirements, reference the guidelines in Table 9-1.
For bidirectional I/O application-specific requirements, reference the guidelines in Table 9-2.
| DESIGN PARAMETER | REQUIREMENTS |
|---|---|
| SDI_IO+, SDI_OUT+ AC-coupling capacitors | 4.7-μF capacitors recommended |
| SDI_IO–, SDI_OUT– AC-coupling capacitors | 4.7-μF capacitors recommended, AC terminated with 75 Ω to VSS. |
| IN0± and OUT0± AC-coupling capacitors | 4.7-μF capacitors recommended |
| Input and Output Terminations | Input and output terminations provided internally. Do not add external terminations. |
| DC power supply decoupling capacitors | 10-μF and 1-μF bulk capacitors; place close to each device. 0.1-μF capacitor; place close to each supply pin. |
| VDD_LDO decoupling capacitors | 1-μF and 0.1-μF capacitors; place as close as possible to the device VDD_LDO pin. |
| MODE_SEL Pin | SPI: Leave MODE_SEL unconnected (Level F) SMBus: Connect 1 k? to VSS (Level L) |
| Input Reclocked Data Rate (SDI_IO in EQ mode or IN0 in CD mode) | 11.88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gbps, or Divide-by-1.001 sub-rates and 270 Mbps. For all other input data rates, the reclocker is automatically bypassed. |
| DESIGN PARAMETER | REQUIREMENTS |
|---|---|
| EQ/CD_SEL Pin | 1 k? to VSS (Level L) when SDI_IO is used as a cable EQ input 1 k? to VIN (Level H) when SDI_IO is used as a cable driver output |
| OUT0_SEL Pin | 1 k? to VSS (Level L) to enable OUT0 for monitoring purposes 1 k? to VIN (Level H) to disable OUT0 (available only in CD mode) |
| SDI_OUT_SEL Pin | 1 k? to VSS (Level L) to enable cable loop-through (EQ mode) or secondary cable output (CD mode) 1 k? to VIN (Level H) to disable cable loop-through (EQ mode) or secondary cable output (CD mode) |