ZHCSIC9D April 2016 – June 2018 LMH1219
PRODUCTION DATA.
The 4-level input configuration pins use a resistor divider to provide four logic states for each control pin. There is an internal 30-kΩ pull-up and a 60-kΩ pull-down connected to the control pin that sets the default voltage at 2/3 x VDDIO. These resistors, together with the external resistor, combine to achieve the desired voltage level. By using the 1-kΩ pull-down, 20-kΩ pull-down, no connect, and 1-kΩ pull-up, the optimal voltage levels for each of the four input states are achieved as shown in Table 1.
| LEVEL | SETTING | RESULTING PIN VOLTAGE |
|---|---|---|
| H | Tie 1 kΩ to VDDIO | VDDIO |
| F | Float (leave pin open) | 2/3 × VDDIO |
| R | Tie 20 kΩ to VSS | 1/3 × VDDIO |
| L | Tie 1 kΩ to VSS | 0 |
Typical 4-Level Input Thresholds: