ZHCSIC9D April 2016 – June 2018 LMH1219
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 4-Level Input Configuration Pins
- 7.3.2 Input Carrier Detect
- 7.3.3 -6 dB Splitter Mode Launch Amplitude for IN0
- 7.3.4 Continuous Time Linear Equalizer (CTLE)
- 7.3.5 Input-Output Mux Selection
- 7.3.6 Clock and Data Recovery (CDR) Reclocker
- 7.3.7 Internal Eye Opening Monitor (EOM)
- 7.3.8 Output Function Control
- 7.3.9 Output Driver Amplitude and De-Emphasis Control
- 7.3.10 Status Indicators and Interrupts
- 7.3.11 Additional Programmability
- 7.4 Device Functional Modes
- 7.5 LMH1219 Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
10.2 Layout Example
The following example demonstrates the high speed signal trace routing to the LMH1219.
- BNC footprint and anti-pad: Consult BNC manufacturer for proper size.
- Anti-pad under passive components.
- 75-Ω single ended trace. Trace width should be similar to that of the IC landing pad (10 mil).
- 100-Ω coupled trace.
- Vias with solder mask.
Figure 41. LMH1219 PCB Layout Example