ZHCSIC9D April 2016 – June 2018 LMH1219
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 4-Level Input Configuration Pins
- 7.3.2 Input Carrier Detect
- 7.3.3 -6 dB Splitter Mode Launch Amplitude for IN0
- 7.3.4 Continuous Time Linear Equalizer (CTLE)
- 7.3.5 Input-Output Mux Selection
- 7.3.6 Clock and Data Recovery (CDR) Reclocker
- 7.3.7 Internal Eye Opening Monitor (EOM)
- 7.3.8 Output Function Control
- 7.3.9 Output Driver Amplitude and De-Emphasis Control
- 7.3.10 Status Indicators and Interrupts
- 7.3.11 Additional Programmability
- 7.4 Device Functional Modes
- 7.5 LMH1219 Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
訂購信息
7.4.2.1.2 SPI Read Transaction Format
A SPI read transaction is 34 bits per device and consists of two 17-bit frames. The first 17-bit read transaction frame shifts in the address to be read, followed by a dummy transaction second frame to shift out 17-bit read data. The R/W bit is 1'b for the read transaction, as shown in Figure 19.
The first 17 bits from the read transaction specifies 1-bit of R/W and 8-bits of address A7-A0 in the first 8 bits. The eight 1’s following the address are ignored. The second dummy transaction acts like a read operation on address 0xFF and needs to be ignored. However, the transaction is necessary in order to shift out the read data D7-D0 in the last 8 bits of the MISO output. As with the SPI Write, the “prime” values on MISO during the first 16 clocks are don’t-care for this portion of the transaction. The values shifted out on MISO during the last 17 clocks reflect the read address and 8-bit read data for the current transaction.
Figure 19. Signal Timing for a SPI Read Transaction