4 Revision History

Changes from Revision C (December 2020) to Revision D (February 2022)

闡明了頻率范圍內的最大通道插入損耗Go
Clarified the description of the clock and data differential output pins.Go
Changed IDx pin voltage from VDD18 to VDD33.Go
Removed normal mode PASS function since PASS is used only in BIST modeGo
Updated the inclusive termonologies for SPI and I2C by changing "master" and "slave" wordingGo
Updated the SPI pin names from "MOSI" to "PICO", "MISO" to "POCI", and "SS" to "CS"Go
Changed the I2S mode names from Slave Mode to Surround Sound Mode, and from Master Mode to Auxiliary Audio ModeGo
Added some missing units for current and voltage Go
Modified the list of compatible devicesGo
Removed PASS from the table since PASS functionality is only used for BIST mode.Go
Corrected the Nyquist Frequency for PCLK 192MHzGo
Added clarifying notes for BIST function.Go
Added a clarifying note on using I2C while PATGEN is enabled.Go
Added new section "Dual Swap"Go
Clarified LVDS mapping namesGo
LVDS Formats table addedGo
Added clarifying notes to LUT contents. Go
Added LUT Programming ExampleGo
Added clarifying notes about I2C access over the BCC Go
Specified which registers are not being reset when digital reset is applied.Go
Changed default value of register 0x01[2] and added clarifying notesGo
Changed default value of register 0x03[7]Go
Changed reset value of register 0x1D, and changed default value for bits [7:4]Go
Changed reset value for registers 0x1E and 0x1F to 0x00Go
Added clarifying note to register 0x22, that surround audio is not supported in repeater mode when 18-bit video mode is enabled.Go
Added minimum value to register 0x26 Go
Changed default value for register 0x45[7:5] and changed to R/W. Added clarifying note. Go
Changed default value for register 0x4B[3:2] and changed to R/W. Added clarifying note.Go
Added clarifying note to CMLOUT function in register 0x57.Go
Changed default value for register 0xF4Go
Corrected the name of the Pattern Generation Application Note in the Related Documentation section. Go

Changes from Revision B (November 2020) to Revision C (December 2020)

添加了特性要點“提供功能安全”Go

Changes from Revision A (January 2016) to Revision B (November 2018)

更改了 PCLK 頻率以支持 192MHz 的更高頻率Go
通過刪除電源節點簡化了典型應用Go
Removed bolded pin description name for power supplies. Go
Added new pin description content to the Pin Functions table Go
Changed the description from VDDIO to V(I2C). Go
Specified in current instead of resistor for all pulldown resistor Go
Removed 200-μA minimum ramp time for PDB pin description. Go
Added the description to clarify the INTB_IN that this pin can be an output driver.Go
Changed pin names from CAP_PLL0 and CAP_PLL1 to RES0 and RES1 respectively. Go
Removed tablenote from the Absolute Maximum Ratings table: For soldering specifications, see product folder at www.ti.com and SNOA549 Go
Added Military/Aerospace tablenote to the Absolute Maximum Ratings table Go
Changed supply voltage maximum for the VDD33 from: 4 V to: 3.96 V Go
Changed VDD12 abs max from 1.8V to 1.44V. Go
Changed supply voltage for the VDDIO from: 4 V to: 3.96 V Go
Added the Added the open-drain voltage, CML output voltage, and FPD-Link III input voltage parameters to the Absolute Maximum Ratings table , open-drain voltage, CML output voltage, and FPD-Link III input voltage parameters to the Absolute Maximum Ratings table Go
Added test conditions to the LVCMOS I/O voltage parameter Go
Spelled out all GPIOs pin name.Go
Combined the ESD ratings into one ESD Ratings table Go
Removed VDD18 test condition from the supply voltage parameter Go
Added the open-drain voltage parameter to the Recommended Operating Conditions table Go
Changed open LDI clock frequency (dual link) maximum from: 170 MHz to: 192 MHz Go
Added the local I2C frequency parameter to the Recommended Operating Conditions table Go
Added test conditions to the supply noise parameter Go
Changed the total power consumption, normal operation test conditions Go
Changed "VDD12 = 1.2 V" to "VDD12 = 1.2 V"Go
Removed the checkerboard vs. PRBS pattern condition and combined typical and worst case together. Go
Added current specs for PCLK 192 MHz. Go
Deleted typical value for Vih and Vil in 3.3V LVCMOS I/O.Go
Split out the test conditions in the 3.3-V and 1.8-V LVCMOS I/O parameters Go
Added strap pin input current parameter to the DC Electrical Characteristics table Go
Deleted typical value for Vih and Vil in 1.8V LVCMOS I/O. Go
Deleted typical value for Vih and Vil in serial control bus Go
Added test conditions to the input high level and input low level parameters Go
Changed "complimentary" to "complementary" Go
Removed tablenote from the AC Electrical Characteristics table: This parameter is specified by characterization and is not tested in production. Go
Changed differential output eye height from: >300 mV to: 300 mV Go
Added input jitter tolerance specs. Go
Removed tablenote from the Timing Requirements table: Parameter is specified by bench characterization and is not tested in production. Go
Changed C_b fast mode plus maximum value from: 550 pF to: 200 pF Go
Removed tablenote from the Switching Characteristics table: Parameter is specified by bench characterization and is not tested in production. Go
Changed Deserializer Eye Diagram graph in the Typical Characteristics sectionGo
Added paragraph explains HSCC mode.Go
Changed transmission distance section and insertion loss tableGo
Changed PCLK frequncy from 96 MHz to 192 MHz in the diagram "2-lane FPD-link Input, Link OpenLDI Output" in the Data-Path Configurations graphicGo
Changed the resistor ratio value for both the Configuration Select (MODE_SEL0) and Configuration Select (MODE_SEL1) tables.Go
Deleted repeated first paragraph LUT contents. Go
Changed pullup power supply node from "VDDIO" to "V(I2C). Go
Updated register table format to the latest TI standards in the Register Maps sectionGo
Changed input value from 1.2 V to 1.2 V in typical application drawings Go
Updated STP diagram. Go
Updated Coax diagramGo
Simplified the diagram by removing power supplies node. Go
Added new design parameters to the Design Requirements section Go
Changed VDD12 in Design Parameters 1.2 to 1.2 Go
Changed CML Interconnect Guidelines section title to FPD-Link III Interconnect Guidelines Go
Added AV Mute Prevention section Go
Added Prevention of I2C Errors During Abrupt System Faults section Go
Moved the Power Sequence graphic to the Power Supply Recommendations Go
Removed power supplies columns and changed the parameters in the Power-Up Sequencing Constraints table according to the diagram. Go
Moved the PCB Layout and Power System Considerations content to the Layout Guidelines section Go
Added Ground and Routing FPD-Link III Signal Traces sections to the Layout sectionGo
Added Added FPD-Link training videos to the Related Documentation section. Go

Changes from Revision * (October 2014) to Revision A (January 2016)

Added shared pins description on SPI pins Go
Added shared pins description on GPIO pins Go
Added shared pins description on D_GPIO pins Go
Added shared pins description on register only GPIO pins. Changed "Local register control only" to "I2C register control only". Go
Added shared pins description on slave mode I2S pins Go
Added shared pins description on Controller mode I2S pins Go
Added legend for I/O TYPEGo
Moved Storage Temperature Range from ESD to Absolute Maximum Ratings table Go
Added ESD Ratings tableGo
Changed IDD12Z limit from 8mA to 30mA per PE re-characterization Go
Changed V_OS from 1.0V to 1.125V Go
Changed V_OS from 1.5V to 1.375V Go
Changed Fast Plus Mode t_SP maximum from 20ns to 50ns Go
Added Image Enhancement Features section Go
Added description to register 0x01[1] "Registers which are loaded by pin strap will be restored to their original strap value when this bit is set. These registers show ‘Strap’ as their default value in this table." Go
Corrected 0x02[7]register default value from "0" to "1" Go
Added to 0x02[7] in Description column "A Digital reset 0x01[0] should be asserted after toggling Output Enable bit LOW to HIGH" Go
Corrected 0x02[4] register default value from 0 to 1 Go
Added "Loaded from remote SER" in register 0x07[7:1] function columnGo
Added "/1" Go
Changed signal detect bit to reserved Go
Changed from Reserved to Rev-ID in register 0x1D Function column Go
Changed from Reserved to Rev-ID Go
On register 0x22 added "(Loaded from remote SER)"Go
Corrected in register 0x24[3] 0: Bist configured through "bit 0" to "bits 2:0" in description Go
Added in register 0x24[2:1] additional descriptionGo
Changed in register 0x24[1] description to "internal" Go
Changed in register 0x24[2] description to "internal" Go
On register 0x28 added "Loaded from remote SER"Go
Added clarification description on register 0x37 MODE_SELGo
Merged on 0x45 bits[7:4} and bits[3:0] default value: 0x08Go
Added Power Sequence section Go