ZHCSEN7D October 2014 – February 2022 DS90UB948-Q1
PRODUCTION DATA
| PIN | I/O, TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| OLDI OUTPUT PINS | |||
| CLK1– CLK1+ |
37 36 |
O, LVDS | Clock differential
output pins This pair requires an external 100-Ω termination for LVDS. Leave unused pins as No Connect or terminate each differential pair with 100 ohms |
| CLK2– CLK2+ |
24 23 |
O, LVDS | |
| D0– D0+ |
43 42 |
O, LVDS | Differential data
output pins This pair requires an external 100-Ω termination for LVDS. Leave unused pins as No Connect or terminate each differential pair with 100 ohms |
| D1– D1+ |
41 40 |
O, LVDS | |
| D2– D2+ |
39 38 |
O, LVDS | |
| D3– D3+ |
35 34 |
O, LVDS | |
| D4– D4+ |
30 29 |
O, LVDS | |
| D5– D5+ |
28 27 |
O, LVDS | |
| D6– D6+ |
26 25 |
O, LVDS | |
| D7– D7+ |
22 21 |
O, LVDS | |
| FPD-LINK III INTERFACE | |||
| RIN0– | 54 | I/O | FPD-Link III RX Port 0 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible FPD-Link III serializer TX through a STP or coaxial cable (see Figure 8-4 and Figure 8-5). It must be AC-coupled per Table 8-1. Leave unused pins as No Connect. Do not connect to an external pullup or pulldown. |
| RIN0+ | 53 | I/O | |
| RIN1– | 59 | I/O | FPD-Link III RX Port 1 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible FPD-Link III serializer TX through a STP or coaxial cable (see Figure 8-4 and Figure 8-5). It must be AC-coupled per Table 8-1. Leave unused pins as No Connect. Do not connect to an external pullup or pulldown. |
| RIN1+ | 58 | I/O | |
| CMF | 55 | I/O | Common mode filter – connect 0.1-μF capacitor to GND |
| I2C PINS | |||
| I2C_SDA | 46 | I/O, OD | I2C Data Input / Output Interface
pin. See Section 7.6.1. Open drain output; this pin must have an external pullup resistor to VI2C DO NOT FLOAT. Recommend a 2.2 kΩ or 4.7 kΩ pullup to 1.8 V or 3.3 V respectively. See I2C Bus Pullup Resistor Calculation (SLVA689). |
| I2C_SCL | 45 | I/O, OD | I2C Data Input / Output Interface
pin. See Section 7.6.1. Open drain output; this pin must have an external pullup resistor to VI2C DO NOT FLOAT. Recommend a 2.2 kΩ or 4.7 kΩ pullup to 1.8 V or 3.3 V respectively. See I2C Bus Pullup Resistor Calculation (SLVA689). |
| IDx | 47 | I, S | I2C Serial Control Bus Device ID
Address Select configuration pin Connect to an external pullup to
VDD33 and a pulldown to GND to create a voltage divider. See Table 7-11. |
| SPI PINS | |||
| PICO (D_GPIO0) |
19 | I/O, PD | SPI Controller Output, Peripheral
Input pin (function programmed through register) It is a multifunction pin (shared with D_GPIO0) with a weak internal pulldown (3μA). Pin function is programmed through registers. If unused, tie to an external pulldown. |
| POCI (D_GPIO1) |
18 | I/O, PD | SPI Controller Input, Peripheral
Output pin (function programmed through register) It is a multifunction pin (shared with D_GPIO1) with a weak internal pulldown (3μA). Pin function is programmed through registers. If unused, tie to an external pulldown. |
| SPLK (D_GPIO2) |
17 | I/O, PD | SPI Clock pin (function programmed
through register) It is a multifunction pin (shared with D_GPIO2) with a weak internal pulldown (3μA). Pin function is programmed through registers. If unused, tie to an external pulldown. |
| CS (D_GPIO3) |
16 | I/O, PD | SPI Peripheral Select pin
(function programmed through register) It is a multifunction pin (shared with D_GPIO0) with a weak internal pulldown (3μA). Pin function is programmed through registers. If unused, tie to an external pulldown. |
| CONTROL PINS | |||
| MODE_SEL0 | 61 | I, S | Mode Select 0
configuration pin Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider. See Configuration Select (MODE_SEL0) Table 7-8. |
| MODE_SEL1 | 50 | I, S | Mode Select 1
configuration pin Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider. See Configuration Select (MODE_SEL1) Table 7-9. |
| PDB | 48 | I, PD | Inverted Power-Down
input pin Typically connected to a processor GPIO with a pulldown. When PDB input is brought HIGH, the device is enabled and internal registers and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN with an weak (>100-kΩ) internal pulldown enabled. PDB should remain low until after power supplies are applied and reach minimum required levels. PDB = 1, device is enabled (normal operation) PDB = 0, device is powered down When the device is in the POWER DOWN state, the LVCMOS outputs are in tri-state, the PLL is shut down, and IDD is minimized. |
| BISTEN | 5 | I, PD | BIST Enable pin 0: BIST mode is disabled 1: BIST mode is enabled It is a configuration pin with a weak internal pulldown (3μA). If unused, tie to an external pulldown. See Section 7.3.15 for more information. |
| BISTC (INTB_IN) |
4 | I, PD | BIST Clock Select pin
(function programmed through register) 0: PCLK 1: 33 MHz It is a multifunction pin (shared with INTB_IN) with a weak internal pulldown (3μA). Pin function is programmed through registers. If unused, tie to an external pulldown. |
| INTB_IN (BISTC) |
4 | I, PD | Interrupt Input pin
(default function). It is a multifunction pin (shared with BISTC) with a weak internal pulldown (3μA). Pin function is programmed through registers. If unused, tie to an external pulldown. The INTB_IN pin may act as an output driver and pull low when PDB is low (see Section 7.3.8). |
| GPIO PINS | |||
| GPIO0 (SDOUT) |
7 | I/O | General Purpose Input / Output 0
pin (default function) default state: logic LOW It is a multifunction pin (shared with SDOUT) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| GPIO1 (SWC) |
8 | I/O | General Purpose Input / Output 1
pin (default function) default state: logic LOW It is a multifunction pin (shared with SWC) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| GPIO2 (I2S_DC) |
10 | I/O | General Purpose Input / Output 2
pin (default function) default state: logic LOW It is a multifunction pin (shared with I2S_DC) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| GPIO3 (I2S_DD) |
9 | I/O | General Purpose Input / Output 3
pin (default function) default state: logic LOW It is a multifunction pin (shared with I2C_DD) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| GPIO9 (MCLK) |
15 | I/O | General Purpose Input / Output 9
pin (default function) default state: logic LOW It is a multifunction pin (shared with MCLK) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| HIGH-SPEED GPIO PINS | |||
| D_GPIO0 (PICO) |
19 | I/O | High-Speed General Purpose Input /
Output 0 pin (default function) default state: tri-state Only available in Dual Link Mode. It is a multifunction pin (shared with PICO) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| D_GPIO1 (POCI) |
18 | I/O | High-Speed General Purpose Input /
Output 1 pin (default function) default state: tri-state Only available in Dual Link Mode. It is a multifunction pin (shared with POCI) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| D_GPIO2 (SPLK) |
17 | I/O | High-Speed General Purpose Input /
Output 2 pin (default function) default state: tri-state Only available in Dual Link Mode. It is a multifunction pin (shared with SPLK) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| D_GPIO3 (CS) |
16 | I/O | High-Speed General Purpose Input /
Output 3 pin (default function) default state: tri-state Only available in Dual Link Mode. It is a multifunction pin (shared with CS) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| REGISTER ONLY GPIO PINS | |||
| GPIO5_REG (I2S_DB) |
11 | I/O | High-Speed General Purpose Input /
Output 5 pin (default function) I2C register control only default state: logic LOW It is a multifunction pin (shared with I2S_DB) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| GPIO6_REG (I2S_DA) |
12 | I/O | High-Speed General Purpose Input /
Output 6 pin (default function) I2C register control only default state: logic LOW It is a multifunction pin (shared with I2S_DA) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| GPIO7_REG (I2S_WC) |
14 | I/O | High-Speed General Purpose Input /
Output 7 pin (default function) I2C register control only default state: logic LOW It is a multifunction pin (shared with I2S_WC) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| GPIO8_REG (I2S_CLK) |
13 | I/O | High-Speed General Purpose Input /
Output 8 pin (default function) I2C register control only default state: logic LOW It is a multifunction pin (shared with I2S_CLK) with a weak internal pulldown (3 μA). Pin function is programmed through registers. See Section 7.3.9. If unused, tie to an external pulldown. |
| SURROUND SOUND (SS) MODE LOCAL I2S CHANNEL PINS | |||
| I2S_WC (GPIO7_REG) |
14 | O | SS Mode I2S Word Clock Output pin
(function programmed through register) It is a multifunction pin (shared with GPIO7_REG). Pin function is programmed through registers. See Section 7.3.13. If unused, tie to an external pulldown. |
| I2S_CLK (GPIO8_REG) |
13 | O | SS Mode I2S Clock Output pin
(function programmed through register) NOTE: Disable I2S data jitter cleaner, when using these pins, through the register bit I2S Control: 0x2B[7]=1 It is a multifunction pin (shared with GPIO8_REG). Pin function is programmed through registers. See Section 7.3.13. If unused, tie to an external pulldown. |
| I2S_DA (GPIO6_REG) |
12 | O | SS Mode I2S Data Output pin
(function programmed through register) It is a multifunction pin (shared with GPIO6_REG). Pin function is programmed through registers. See Section 7.3.13. If unused, tie to an external pulldown. |
| I2S_DB (GPIO5_REG) |
11 | O | SS Mode I2S Data Output pin
(function programmed through register) It is a multifunction pin (shared with GPIO5_REG). Pin function is programmed through registers. See Section 7.3.13. If unused, tie to an external pulldown. |
| I2S_DC (GPIO2) |
10 | O | SS Mode I2S Data Output (function
programmed through register) It is a multifunction pin (shared with GPIO2). Pin function is programmed through registers. See Section 7.3.13. If unused, tie to an external pulldown. |
| I2S_DD (GPIO3) |
9 | O | SS Mode I2S Data Output (function
programmed through register) It is a multifunction pin (shared with GPIO3). Pin function is programmed through registers. See Section 7.3.13. If unused, tie to an external pulldown. |
| AUXILIARY AUDIO (AA) MODE LOCAL I2S CHANNEL PINS | |||
| SWC (GPIO1) |
8 | O | AA Mode I2S Word Clock Output pin
(function is programmed through registers) (Pin is shared with GPIO1) It is a multifunction pin (shared with GPIO1). Pin function is programmed through registers. See Section 7.3.13. If unused, tie to an external pulldown. |
| SDOUT (GPIO0) |
7 | O | AA Mode I2S Data Output pin
(function is programmed through registers) (Pin is shared with GPIO0) It is a multifunction pin (shared with GPIO0). Pin function is programmed through registers. See Section 7.3.13. If unused, tie to an external pulldown. |
| MCLK (GPIO9) |
15 | O | AA Mode I2S System Clock Output
pin (function is programmed through registers) (Pin is shared with GPIO9) It is a multifunction pin (shared with GPIO9). Pin function is programmed through registers. See Section 7.3.13. If unused, tie to an external pulldown. |
| STATUS PINS | |||
| LOCK | 1 | O | Lock Status Output pin LOCK = 1: PLL acquired lock to the reference clock input LOCK = 0: PLL is unlocked |
| PASS | 7 | O | BIST mode status output pin
(BISTEN = 1) PASS = 1: No error detected PASS = 0: Error detected |
| POWER and GROUND | |||
| VDD33_A, VDD33_B |
56 31 |
P | 3.3-V (±10%) supply. Power to on-chip regulator. Requires 10-μF, 1-μF, 0.1-μF, and 0.01-μF capacitors to GND. |
| VDDIO | 3 | P | LVCMOS I/O power supply: 1.8 V (±5%) OR 3.3 V (±10%). Requires 10-μF, 1-μF, 0.1-μF, and 0.01-μF capacitors to GND. |
| VDD12_LVDS VDDP12_LVDS VDDL12_0 VDDL12_1 VDDP12_CH0 VDDR12_CH0 VDDP12_CH1 VDDR12_CH1 |
20 32 6 44 51 52 60 57 |
P | 1.2-V (±5%) supply. Requires 10-μF, 1-μF, 0.1-μF, and 0.01-μF capacitors to GND at each VDD pin. |
| CAP_I2S VDD25_CAP |
2 33 |
D | Decoupling capacitor connection for on-chip regulator. Recommend to connect with a 0.1-μF decoupling capacitor to GND. |
| VSS | DAP | G | DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 32 vias. |
| OTHER PINS | |||
| CMLOUTP CMLOUTN |
62 63 |
O | Channel Monitor Loop-through
Driver differential output pins Route to a test point or a pad with
100-Ω termination resistor between pins for channel monitoring
(recommended). See Figure 8-1
or Figure 8-2.
|
| RES0 RES1 |
49 64 |
- | Reserved pins. 0.1-μF decoupling capacitor could be placed to GND. May be left floating as No Connect pins. |
The following definitions
define the functionality of the I/O cells for each pin. I/O TYPE:
|