ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
RX port-specific register. The FPD-Link III Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7 | I2C_PASS_THROUGH _ALL | R/W | 0 | I2C Pass-Through All Transactions 0: Disabled 1: Enabled |
| 6 | I2C_PASS_THROUGH | R/W | 0 | I2C Pass-Through to Serializer if decode matches 0: Pass-Through Disabled 1: Pass-Through Enabled |
| 5 | AUTO_ACK_ALL | R/W | 0 | Automatically Acknowledge all I2C writes independent of the forward channel lock state or status of the remote Acknowledge 1: Enable 0: Disable |
| 4 | BC_ALWAYS_ON | R/W | 1 | Back channel enable 1: Back channel is always enabled independent of I2C_PASS_THROUGH and I2C_PASS_THROUGH_ALL 0: Back channel enable requires setting of either I2C_PASS_THROUGH and I2C_PASS_THROUGH_ALL This bit may only be written via a local I2C master. |
| 3 | BC_CRC_GENERATOR _ENABLE | R/W | 1 | Back Channel CRC Generator Enable 0: Disable 1: Enable |
| 2:0 | BC_FREQ_SELECT | R/W/S | Strap | Back Channel Frequency Select 000: 2.5 Mbps (default for DS90UB633A-Q1 compatibility) 001: Reserved 010 - 111 : Reserved 010: 10 Mbps 011: Reserved 100: Reserved 101: Reserved 110: Reserved 111: Reserved Note that changing this setting will result in some errors on the back channel for a short period of time. If set over the control channel, the Deserializer should first be programmed to Auto-Ack operation to avoid a control channel timeout due to lack of response from the Serializer. The 20 Mbps and 100 Mbps modes should not be used when the internal reference clock is running at 100 MHz. This includes operation with either CSI_PLL_CTL:REF_CLK_MODE set to 1 or CSI_PLL_CTL:CSI_TX_SPEED set for 400 Mbps operation. |