ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
Upon initialization GPIO0 through GPIO7 are enabled as inputs by default. Each GPIO pin has an input disable and a pulldown disable control bit with exception of the open-drain GPIO3 pin. By default, the GPIO pin input paths are enabled and the internal pulldown circuit for the GPIO is enabled. The GPIO_INPUT_CTL (Table 7-33) and GPIO_PD_CTL (Table 7-176) registers allow control of the input enable and the pulldown, respectively. For example to disable GPIO1 and GPIO2 as inputs you would program in register 0x0F[2:1] = 11. For most applications, there is no need to modify the default register settings for the pull down resistors. The status HIGH or LOW of each GPIO pin 0 through 7 may be read through the GPIO_PIN_STS register 0x0E (Table 7-32). This register read operation provides the status of the GPIO pin independent of whether the GPIO pin is configured as an input or output.